Regardless of the truth of the details, 28nm has been a real challenge, particularly in the initial ramp up phase. This is more sanely evidenced in the increasing amount of DFM activities being pushed to the designer at these nodes. Things like litho checking, smart fill, pattern based checks, and restricted design rule checks have migrated from recommended to required. This is evidence enough that many of the second and third order effects on yield are becoming first order. Strict adherence and effort spent optimizing these DFM issues in the design phase is probably what is causing such different results on different chips. All designs are not the same from a DFM perspective.
It sounds like there is no clear story here, one says no yield and another says on target for defect density. It could mean the 0% yield is on track with what they expect for defects at this point. I am sure that they are closing guarding the real numbers. Only time will tell, I am rooting for success as it can only help drive costs down overall in the market.
Samsung stays ahead of TSMC in this regard because they always start a new node with memory before going to processors. For memory Samsung is already at 20 nm. Samsung's A6 for Apple is already at 28 nm ( only in Austin, NOT So. Korea )
In the last few years TSMC has come through as being a little too cocky about their market share and at Technical Conferences sounded almost "Big Brother" ish.
Samsung's spending of 10s of billion $ in 2012 does not bode well for TSMC lead in Foundry. In fact TSMC is already out in the public back pedalling on their CapEx siting low growth in demand.
What happens now if nVidia or even Qualcomm ( current large customers of TSMC ) now jump ship ( Samsung, even Intel ?? ) in order to stay competitive with A6 Quad Core ?
Since most of the large fabless companies are satisfied with TSMC 28nm process, the low yield issues of some companies are potentially due to design related process issues. It can be fixed by design/process expert after review the layout.
It looks like xilinx was really happy with tsmc 28 nm, so it's probably rushed designs that's the problem.
I think we may potentially see many fabless semiconductor companies talk about moving to UMC and/or Samsung for 22nm if TSMC has a setback at 28nm. But much of this will be idle talk to try and get TSMC to lower prices since nobody else has enough production capacity at this point. Most 28nm designs simply are not ready for production level tapeout since the process and IP are immature for 2011 and 2012. I suspect much blame also resides within TSMC's customers for the failure since just about everyone does test chips on new processes for characterization before launching production designs.
No mention of UMC 28nm in this article, but EE Times article from last year indicated TI using UMC as their lead foundry for 28nm. I assume other chip companies have similar multi-source foundry strategies.
It will be interesting to see which foundry can work out thier 28nm yield issues first and how this translates to application processor and GPU market share in 2013.
"While problematic, TSMC have enough of a capital cushion to withstand such losses."
That is the problem. The big three have enough capital cushion for anything. They have no need for innovation except for their own. You have to turn to FTC to get anything, like in the Univ. of New Mexico vs. TSMC case. It is killing the ecosystem.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.