The original analyst commentary on TSMC production issues triggered an remarkable outpouring of reader commentary. Growing pains at new resolutions are common - I guess perceptions are important enough that TSMC felt it was worthwhile to provide a level of detail in their response.
Both Samsung and TSMC (and also UMC at smaller scale) are ramping up 28 nm.
Morris Chang stated a long time ago that the move to 28nm is almost twice as capital intensive compared to previous node.
Paying attention to Chang paid off handsomely for me.
Samsung is spending aggressively on logic.
But so does: TSMC is increasing its monthly 12 inch wafer start capacity by 12 000 wafers (Fab 12) and 11 666 wafers (Fab 14).
(you can verify by checking TSMC management reort for Q4 2011 @TSMC.com)
That's a lot
TSMC has to deal with far more customers (designs)compared to Samsung whose production is to a large portion captive.
Besides TSMC already made the transition to "gate last"
From WSJ in regards to Samsung
We now believe 300-millimeter wafer start demand for just the A-series processor chips used in Apple's iPhones and iPads was about 52,000 wafer starts per month (WSPM) in fourth-quarter 2011 (up 400%-plus year-over-year), above our prior estimate of about 42,000 WSPM. We now expect wafer demand to ...
I read "that defect density reduction is on track for the 28-nm node and ahead of where TSMC was with 40/45-nm process technology at an equivalent stage in its roll out" and wonder our loud: what does this mean? I am sure that no-one wants to advertise defect density rates in a new process! I am not sure that it can quell the questions regarding the current ability to produce volume in 28nm. I would me more excite to hear about the numbers of devices shipped (instead of the revenue), if you ship one working device (I am sure that this is not the case) and sell it for 100million that could show great profit but not capacity. The numbers of devices shipped and volume capacity numbers would go a long way to quieting the noise makers.
I think that at these advanced nodes with all the DFM sensitivities, the yield variability is becoming increasingly in the hands of the designer. The variabilty between yield on the different designs points to this.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.