Even after the gate first fiasco GloFo keeps blindly following IBM for technical decisions. To catch up after these embarrassing ( fatal ? ) technical decisions GloFo needs people with a successful track record at the top. Yet GloFo is full of people from Motorola Semiconductor Fabs in Autin that failed to keep up and withered away into Freescale. GloFo CTO is from Motorola and does not even have a PhD. Just compare that with the TSMC bench.
Qualcomm, TI, and others did not use much high-k/metal gate technology at 28nm because of a lack of maturity at all foundries. Relatively low yields, relatively high costs, caused them to stick with a largely non-high-k gate stack at 28nm. This has little or nothing to do with gate-first, gate-last, GlobalFoundries or TSMC.
In order to ramp the product in 32nm and below, the fabless design house need the design expertise to show them how to modify the current design to fit the advanced process, especially for HKMG one. There are few high order effects never shown in bulk process before. GF needs someone to help AMD migrated to 28nm Gate-First HKMG technology.
He can say anything he wants but without data to back it up, it's just a propaganda to hide his real issues. maybe he does not even know what the real issues he is facing. GF lost credibility in a big time. customers will know whether he is telling us truths or not.
Some relevant quotes from an article "That's Two For Intel" published by Tom's hardware.
Supposedly QCOM is not even using high -k /metal gate...
Importantly, TSMC’s decision to go with gate-last (following Intel's approach) is steeped in history, according to the company’s senior VP in charge of R&D. Part of the reason why gate-first manufacturing results in low yields is that you have to control threshold voltage carefully, since the N- and P-channels use the exact same metal. The semiconductor industry tried to carefully control the voltage this way two decades ago and found it very difficult. The gate-last approach doesn’t require the same control because the metal for the P channel is different than the metal for the N channel. You lose some density, but yields are a lot higher, and the easiest way to lose a fight is to not show up at all. It’s not trivial to switch a design from gate-first to gate-last. It requires additional redesign time. To that end, you can’t just change your order from Globalfoundries to TSMC by checking a different box on a form.
It seems that Qualcomm figured out it can’t get the yields it needs on a gate-first approach. At the 2010 International Electron Devices Meeting held in San Francisco, the company stated that it wouldn’t be using high-k/metal gate technology for the majority of its 28 nm products. This is a big disadvantage for Qualcomm.
You have Qualcomm, which faces challenges on the manufacturing side due to gambling on gate-first high-k and now being forced to go with standard silicon,
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.