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There is a "temptation" on the part of Foundries to sidestep yield issues at 28 nm by going back to say 45 nm and partition the SoCs into several layers and then connect them with TSV.
Samsung on the other hand I believe is off and running in Austin at 28 nm for A6.
@chipmonk: on the contrary, lack of real estate is one of the major drivers for stacking in smartphones.
On your last point, Micron is part of the Hybrid Memorycube consortium:
Samsung is also a (founding?) member.
@rick.merritt: assuming your'system' definition refers to a product serving homogeneous or heterogeneous functions while utilizing 2.5D/3D stacking, it will be the future of that system's design. But I would argue that that its function, whether partial or in full, must be complemented by the appropriate value addition in software. That, I believe, is the next generation of 'ASIC' startups!
I "feel" that the Apple vs Samsung tangle could turn out to be one of the biggest factors in how 3D TSV implementation and TSMC comes out in the Smartphone segment. There is a "temptation" on the part of Foundries to sidestep yield issues at 28 nm by going back to say 45 nm and partition the SoCs into several layers and then connect them with TSV. Samsung on the other hand I believe is off and running in Austin at 28 nm for A6.
Re: connecting Memory to APs by TSVs,the bandwidth needs would not become acute for a couple of years.