Embedded Systems Conference
Breaking News
Comments
yalanand
User Rank
Author
re: Lines blurring between digital, analog design worlds
yalanand   2/1/2012 6:12:23 AM
NO RATINGS
Many companies tried to automate the analog design flow (both schematic and layout) and failed. Things like small mismatch in the design can severely affect the performance of the analog designs. Moreover many companies are still using old-reliable analog processes and are reluctant to move to the new processes.

mcgrathdylan
User Rank
Author
re: Lines blurring between digital, analog design worlds
mcgrathdylan   2/1/2012 6:47:13 AM
NO RATINGS
@yalanand- Why are they reluctant to move to new processes?

goafrit
User Rank
Author
re: Lines blurring between digital, analog design worlds
goafrit   2/1/2012 9:49:52 PM
NO RATINGS
Cost and many unknown. If you have a product that has good yield in process A and process B is unknown, it makes no sense to risk that pipeline.

Reid Wender
User Rank
Author
re: Lines blurring between digital, analog design worlds
Reid Wender   2/3/2012 8:31:54 PM
NO RATINGS
New (ie smaller geometries) have fueled digital innovation by allowing us to pack more and more digital transistors into the same silicon area. Analog "in general" doesn't scale quite the same so going to smaller geometries doesn't make the circuit smaller and less expensive. These smaller geometry nodes also have thinner oxides and lower operating voltages so it is often more difficult to design high performance analog at these smaller nodes. That's why you hear a lot of folks saying "More than Moore" these days because a lot of really cool analog and mixed signal designs are being done at the older 0.35u and 0.18u nodes.

old account Frank Eory
User Rank
Author
re: Lines blurring between digital, analog design worlds
old account Frank Eory   2/1/2012 11:46:21 PM
NO RATINGS
I would take exception to the statement that 70% of today's chips are mixed-signal. IMHO, the true number is 100%. Even (or especially) the most gargantuan digital SoC at least has a PLL or two, some DDR I/Os, and other cells that it would be a stretch to refer to as "digital." Yes, the toolsets are very different and there is no question that the bulk of EDA innovation over the last couple decades has been on the digital side. The really interesting part, and a big divergence of methodologies, comes at the chip top level where all the blocks get integrated. In a Big D/Little A chip, the integration is done in a "digital" P&R tool and the analog designers just deliver their blocks (cells), however large or small -- data converters, PLLs, I/O buffers, voltage regulators or whatever. In a Big A/Little D chip, it's the other way around -- the "digital" blocks are treated as cells, like any analog cell, and the whole thing gets integrated into a full chip in an "analog" P&R tool. To add another level of complexity and weirdness, none of the "analog" blocks are truly analog -- there are always some digital standard cells in there too. This creates interesting problems for incorporating that loose logic into scan chains and making the whole thing ATPG-tool-friendly. The analog designers don't know the digital tools and the digital designers don't know the analog tools, so there need to be at least a few people who could rightly be called AMS designers -- those who can play in both sandboxes, to try to cobble the whole mess together into something that is thoroughly verified and tapeout-worthy.

mcgrathdylan
User Rank
Author
re: Lines blurring between digital, analog design worlds
mcgrathdylan   2/2/2012 6:53:19 AM
NO RATINGS
Well said Frank. Thanks for chiming in as always.

PV-Geek
User Rank
Author
re: Lines blurring between digital, analog design worlds
PV-Geek   2/11/2012 10:35:21 PM
NO RATINGS
With the maturing of 3D-IC processing and design tool capabilities, it will be interesting to see if more companies begin migrating the analog portions to separate die/process and then integrating them vertically.



Radio
LATEST ARCHIVED BROADCAST
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
Special Video Section
The LTC®6363 is a low power, low noise, fully differential ...
Vincent Ching, applications engineer at Avago Technologies, ...
The LT®6375 is a unity-gain difference amplifier which ...
The LTC®4015 is a complete synchronous buck controller/ ...
10:35
The LTC®2983 measures a wide variety of temperature sensors ...
The LTC®3886 is a dual PolyPhase DC/DC synchronous ...
The LTC®2348-18 is an 18-bit, low noise 8-channel ...
The LT®3042 is a high performance low dropout linear ...
Chwan-Jye Foo (C.J Foo), product marketing manager for ...
The LT®3752/LT3752-1 are current mode PWM controllers ...
LED lighting is an important feature in today’s and future ...
Active balancing of series connected battery stacks exists ...
After a four-year absence, Infineon returns to Mobile World ...
A laptop’s 65-watt adapter can be made 6 times smaller and ...
An industry network should have device and data security at ...
The LTC2975 is a four-channel PMBus Power System Manager ...
In this video, a new high speed CMOS output comparator ...
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...