Many companies tried to automate the analog design flow (both schematic and layout) and failed. Things like small mismatch in the design can severely affect the performance of the analog designs. Moreover many companies are still using old-reliable analog processes and are reluctant to move to the new processes.
New (ie smaller geometries) have fueled digital innovation by allowing us to pack more and more digital transistors into the same silicon area. Analog "in general" doesn't scale quite the same so going to smaller geometries doesn't make the circuit smaller and less expensive. These smaller geometry nodes also have thinner oxides and lower operating voltages so it is often more difficult to design high performance analog at these smaller nodes. That's why you hear a lot of folks saying "More than Moore" these days because a lot of really cool analog and mixed signal designs are being done at the older 0.35u and 0.18u nodes.
I would take exception to the statement that 70% of today's chips are mixed-signal. IMHO, the true number is 100%. Even (or especially) the most gargantuan digital SoC at least has a PLL or two, some DDR I/Os, and other cells that it would be a stretch to refer to as "digital."
Yes, the toolsets are very different and there is no question that the bulk of EDA innovation over the last couple decades has been on the digital side.
The really interesting part, and a big divergence of methodologies, comes at the chip top level where all the blocks get integrated.
In a Big D/Little A chip, the integration is done in a "digital" P&R tool and the analog designers just deliver their blocks (cells), however large or small -- data converters, PLLs, I/O buffers, voltage regulators or whatever. In a Big A/Little D chip, it's the other way around -- the "digital" blocks are treated as cells, like any analog cell, and the whole thing gets integrated into a full chip in an "analog" P&R tool.
To add another level of complexity and weirdness, none of the "analog" blocks are truly analog -- there are always some digital standard cells in there too. This creates interesting problems for incorporating that loose logic into scan chains and making the whole thing ATPG-tool-friendly.
The analog designers don't know the digital tools and the digital designers don't know the analog tools, so there need to be at least a few people who could rightly be called AMS designers -- those who can play in both sandboxes, to try to cobble the whole mess together into something that is thoroughly verified and tapeout-worthy.
With the maturing of 3D-IC processing and design tool capabilities, it will be interesting to see if more companies begin migrating the analog portions to separate die/process and then integrating them vertically.
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