very well written, look fwd to reading part II, would be interested in the author's thoughts on how die stacking by 3D TSV will upset the current deadlock ( CPU by smaller transistors vs SoCs by ?? transistors ).
I agree that scaling is hitting physical and economic limits and that innovation will likely be centered on extending the life of an existing geometry. Yet, I would like to suggest that the more effective path to using existing manufacturing tools, process technology, transistor structure, etc. is to use monolithic 3D. NAND vendors are already going there and many should follow. The advantages of monolithic 3D are quite significant in device integration, power and performance, and will not need new transistor technology
Hi Zvi, don't you think there needs to be a fundamental shift in IC vendors' business model -that with more progress in SoC and 3D IC's (monolithic & stacking), software is an important component of the offering? To that end, shouldn't the IC companies be working to provide application platforms for developers to spring-off of? I know some of them do but it is inadequate and certainly not accelerating the innovation we all like to see in 3D.
@Pushkar Ranade: great writeup! I hope you continue to post on EE Times.
I agree with you. From the typical usage model of end user, now they don't know why they need such a high performance CPU. The reason why they buy a PC is because PC helps them to get information from internet, play some casual game.
Before a new popular usage case is found, such as popular AI usage at home, cpu performance is engough. While the other factors, such as disk speed, wireless, power, cost, total system size, are the impact factor for the end user.
As internet development, people are much more earier to find the different architectur software, so architecture restriction becomes a less restricted factor.
As the future for human being is to collabration not to fight, so the SOC represents the internal desired spirit of human. Thus can bring more innovation and reduce cost.
Well written! The major rule for wafer fabs is Take no Risks--protect and preserve that huge capital investment so you can pay it down. Change gets equated to risk, especially for wafer fab managers and product developers. So, what’s least risky among the choices of continued scaling, new devices/architectures, 3DIC with TSV, or monolithic 3DIC? I try to parse the variables in a blog post: http://www.monolithic3d.com/2/post/2012/01/is-monolithic-3d-ic-less-risky-than-scaling-or-tsv.html
Thanks all for the comments.
Today, on-chip integration is the ideal solution for cost, power, form factor and reliability. Die stacking and TSV are viable options to extend the life of CMOS once traditional scaling ends. A key pre-requisite for die-stacking is that total package thermal design power (TDP) needs to be low. Hence, the power dissipation of each die/layer needs to be minimized before they can be stacked – which is an even bigger issue for stacked die than for traditional monolithic solutions. Another consideration is price point of stacking compared to more on-chip integration.
I think this is all very interesting... clearly we have a growing problem in our ability to advance processor performance. However, I'm of the opinion that we can't overcome this with better transistors (at least not for long). We need a new architectural paradigm - the traditional approaches are fundamentally out-dated. My bet is on highly efficient, small massively paralleled manycores...
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