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DrFPGA
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re: ST adds 32-bit MCU to 9-axis inertial sensor
DrFPGA   2/25/2012 9:16:10 PM
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Now if we can just get it powered from energy harvesting from motion and/or e-fields that would be a great building block.

Paul911
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re: ST adds 32-bit MCU to 9-axis inertial sensor
Paul911   2/10/2012 1:02:23 AM
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Circuitcode, STMicro is europen and not US... In fact STMicro close down few of its fabs in US few years back... R&D mostly in euro and manufacuting mostly in asia.. dont see US in this equation..

Robotics Developer
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re: ST adds 32-bit MCU to 9-axis inertial sensor
Robotics Developer   2/9/2012 9:06:46 PM
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I would love to know what the cost will be? The size would be nice to know as well as is there a case? I could see this as a great building block for a robot navigation system. Can't wait to see them out!

Circuitcode
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re: ST adds 32-bit MCU to 9-axis inertial sensor
Circuitcode   2/9/2012 8:56:20 PM
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This product is an important innovative member of a "disruptive technology" group that is going to reinvent the American economy and bring back the "rags to riches" engineering garage shops - hang on to your hats folks - we are in for one heck of a ride - and Bravo to STMicro and all of the other U.S. Engineering Technology companies that are cleverly and bravely leading us into the next American Economic Boom.



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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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