Not doing the HKMG certainly makes things easier. If there are a good number of customers that can live with the leakage then this could be good money for UMC. It all depends on how much volume they can get.
Interesting to note that UMC had "smoother-than-expected R&D and pilot run," is it because it took precaution while building its 28nm process or was it plain lucky ? I am sure it would have learnt some lessons from TSMC/GF's mistakes when implementing 28nm process.
Does TI not care about the leakage / power dissipation for their OMAP built by UMC with ye olde polysilicon/silicon oxynitride gate stack rather than HKMG like TSMC / GloFo would have at 28 nm LP ? Perhaps this is just a stop gap / get a foot in the door for a OEM ( A?) who can't wait till UMC gets its HKMG ready at 28 nm.
Well, their 28nm is a conventional gate stack process (poly Si gate with SiON gate oxide) and a far more sophisticated high-k dielectric and metal gate process which is the main stream for TSMC and Intel, IBM.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.