Unfortunately, refining tools and flows requires incorporation of lessons learned, and this is true for almost every new process node. It's a real conundrum, because you don't want to be the first one to tape out a big SoC in the latest process, but time to market pressures don't give you much leeway to let others blaze the trail ahead of you.
For current synthesis and analysis tools, they haven't addressed critical issues for nanotechnology For example, the product leakage is often 2X-4X higher than estimation because it is due to incorrect power model. The high design margin (20%-30%) in current SSTA is due to improper DFM setup, the actual margin can be reduced by half.
Perhaps I could be even bolder and suggest that verification is much like the drug industry. Even if there were a cure, it is more profitable to sell things that work on the symptoms which keeps the customer coming back for more.
Blog Make a Frequency Plan Tom Burke 17 comments When designing a printed circuit board, you should develop a frequency plan, something that can be easily overlooked. A frequency plan should be one of your first steps ...