I think the concern is that with the expense of the fancy litho tools, most fabs would only have 1 or 2 initially. Then when you have all of the critical layers needing to go through the tool multiple times, (active, poly, contact, metals and vias) you end up with wafers just queued behind the litho tool all_the_time - because you don't just have 1 lot at a time running in your fab.
A healthy mix of technologies will be required. Who will make the masks for Imprint technology or inspect and repair them 1x!!
Who will pattern the base structures for directed self assembly, repetitive patterns only??
It might work for memory cells, others?
Rapid prototyping and critical layers of the 1xnm and 2xnm nodes, E-Beam dirct write will be the solution.....no masks, easy to change, or simulate process changes, adapt depending on the flow changes across the wafer..
A lot of challenges ahead....smart device integration might be a better way to improve the performance of devices, not just scaling!!
If only a small fraction of the chip layers get multiple patterning or double patterning, and most design rules on the SOC are very loose, the extra costs will be diluted. So the "worst case" scenario shouldn't be so bad.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.