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driverblock
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re: Analyst dissects Intel Haswell's transactional memory
driverblock   2/22/2012 4:05:08 PM
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Really? Open up Task Manager or Activity Monitor on your laptop and see how many threads are running in your routine applications.

resistion
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re: Analyst dissects Intel Haswell's transactional memory
resistion   2/19/2012 5:55:25 AM
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The average notebook user doesn't routinely run parallel programs. So this only makes sense for servers and workstations.

DrFPGA
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re: Analyst dissects Intel Haswell's transactional memory
DrFPGA   2/18/2012 11:20:46 PM
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"Without substantially rewriting code". If this means any amount of code rewrite the benefit needs to be large. Any benchmark data available on similar schemes?

selinz
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re: Analyst dissects Intel Haswell's transactional memory
selinz   2/18/2012 10:14:37 PM
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Well, it sounds like it is still putting an arbitrator between the memory and the process. A "take a number and wait your turn" idea... But in this case, the arbitrator is on the memory device...

Les_Slater
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re: Analyst dissects Intel Haswell's transactional memory
Les_Slater   2/17/2012 4:54:06 PM
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In the system proposed at DEC there were process transaction ID tags sent with memory requests. For example a read request would include the requester process ID along with the address or address range. This would be queued in the memory system and got to when it could. When delivering requested data the memory system would identify who requested it and the particular request.

Les_Slater
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re: Analyst dissects Intel Haswell's transactional memory
Les_Slater   2/17/2012 4:29:25 PM
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I was hired by DEC as a Principal Engineer in early 1987 to implement a transactional memory. It was to be dual port to be shared between 2 of their XMI buses. One bus to connected to a Prism RISC and the other to their Lynx graphic pipeline. The concept was new to me and I found it quite interesting. The project was cancelled because the graphic pipeline design could not meet performance objectives.

t.alex
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re: Analyst dissects Intel Haswell's transactional memory
t.alex   2/17/2012 2:43:15 PM
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Is it like memory with some capability of transactional database?



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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