I have been hearing about designers ignoring DFT since the 90s, and yet on every design team I have been a member of, DFT was always a major task and was addressed up front -- as a much a part of the chip requirements as any functional requirements.
You're right, analog testing is still lacking automation and this is a big problem in reducing test time for AMS SoCs. Hopefully the EDA community will put some effort into that.
For too long designers have focussed on getting every bit of functionality and relegated test to the backend. However, DFT is taking foothold in almost all design groups, and helping ease the manufacturing problem. Most of DFT technology has been developed to tackle digital testing, and analog, m/s testing is still a problem, not well-defined and left to smart engineers to come up with solutions. Need more work in these areas to automate testing of SoCs populated by a mix of digital, analog, m/s cores and logic.
Increasing no of peripherals and cores puts the "design for test" in a critical situation as the area covered by the test sets increases then the required by the actual chip. But this will be solved as the "Design for Test" is a hot topic among the researchers.
Testing and debugging Silicon Chips is much more complicated as compared to software programs. If the design does not work out there is no means of debugging and correcting once done. All the tests are made in simulation environment, where as in case of software you can come with as many versions of a simple .dll as well.
Fundamentally, testing and debugging silicon chips is the same problem as testing and debugging software programs. The only difference is that one ends up in silicon and wires whereas the other is stored in magnetic domains. Start by studying best practices in software programming and quality control.
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