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old account Frank Eory
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re: Test problems grow as chip integration increases
old account Frank Eory   2/20/2012 11:32:08 PM
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I have been hearing about designers ignoring DFT since the 90s, and yet on every design team I have been a member of, DFT was always a major task and was addressed up front -- as a much a part of the chip requirements as any functional requirements. You're right, analog testing is still lacking automation and this is a big problem in reducing test time for AMS SoCs. Hopefully the EDA community will put some effort into that.

scanman
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re: Test problems grow as chip integration increases
scanman   2/20/2012 10:49:12 PM
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For too long designers have focussed on getting every bit of functionality and relegated test to the backend. However, DFT is taking foothold in almost all design groups, and helping ease the manufacturing problem. Most of DFT technology has been developed to tackle digital testing, and analog, m/s testing is still a problem, not well-defined and left to smart engineers to come up with solutions. Need more work in these areas to automate testing of SoCs populated by a mix of digital, analog, m/s cores and logic.

MSSN
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re: Test problems grow as chip integration increases
MSSN   2/19/2012 12:31:22 PM
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Breakpoints and infinite probes are a big difference between software and silicon debugging

Kinnar
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re: Test problems grow as chip integration increases
Kinnar   2/18/2012 11:08:20 AM
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Increasing no of peripherals and cores puts the "design for test" in a critical situation as the area covered by the test sets increases then the required by the actual chip. But this will be solved as the "Design for Test" is a hot topic among the researchers.

Kinnar
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re: Test problems grow as chip integration increases
Kinnar   2/18/2012 11:05:53 AM
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Testing and debugging Silicon Chips is much more complicated as compared to software programs. If the design does not work out there is no means of debugging and correcting once done. All the tests are made in simulation environment, where as in case of software you can come with as many versions of a simple .dll as well.

DrQuine
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re: Test problems grow as chip integration increases
DrQuine   2/18/2012 4:10:00 AM
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Fundamentally, testing and debugging silicon chips is the same problem as testing and debugging software programs. The only difference is that one ends up in silicon and wires whereas the other is stored in magnetic domains. Start by studying best practices in software programming and quality control.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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