Good description in the article - it makes a lot of sense.
Most logic is synchronously clocked. Your approach seems to keep the states latched (in the virtual wires) while the logic is reconfigured to process other signals.
The reduced wiring complexity by treating time and space routing as interchangeable is very clever.
This offers a level in between standard logic (with gates performing only one function, often idle) and microprocessors (gates being re-used for different functions over time, at lower program speeds).
Wishing you the best success with it!
A useful way to think of this question of power consumption is to consider two identical functions. One implemented using 8 LUTs each operating at 200 MHz, and the second using only 1 LUT operating at 1.6 GHz. If interconnect capacitance were the same in both cases, then power consumption would be identical. Of course in a 3D device interconnects are shorter, so in fact there’s a power advantage for the second faster implementation.
Hi Kris, I like to emphasize the "damn fast in re-configuring your FPGA". Either the reconfiguation clock is very fast (1.6GHz?) or the system clock is very slow. For either case, this 3DFPGA burns much higher power than traditional FPGA's. No perfect solution here.
thank you @abismuth, fascinating technology: "By storing multiple gate configurations on chip, Tabula’s devices can completely reconfigure their fabrics up to 1.6 billion times per second"
any chance someone from Tabula would be interested in presenting it at CMOS emerging technologies event to be held in Vancouver in July? (www.cmoset.com)...I am the conference chair...pls contact me at firstname.lastname@example.org
Great discussion about how our Spacetime 3D architecture works.
If you are interested in knowing more about it you can read this very good article written by Tom Halfhill at Microprocessor Report: http://www.tabula.com/news/M11_Tabula_Reprint.pdf
If you have more questions you can also contact me directly or through our website (www.tabula.com).
You can imagine that this is like PC with disc cache memory. Theoretically, it could have much larger gate count under a small footprint. However, it affects the performance greatly, also 1.6GHz clock generates a lot of more power than expected, during this "on-the-fly" reconfigurations.
A Book For All Reasons Bernard Cole1 Comment Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...