No tools are required for extracting inductance. The Cyclos IP that is provided has been characterized in your process and simulation/verification models are provided. Users don't have to extract inductance so no tools are required.
And yes, designing a resonant clock mesh is very SPICE simulation intensive. Fortunately many EDA vendors have produced new SPICE simulators that have much greater capacity and throughput - so it is possible to simulate/verify a resonant clock mesh in a reasonable/timely manner.
I've gotten several questions privately that I thought I would share with the rest of you since they seemed common to many people.
1. No special libraries or processes are required. Cyclos RCMs work with standard PDKs and does not require inserting any special cells.
2. Reliability may actually be improved due to the reduction in metal migration potential in the clock distribution network. With RCMs, current flows bidirectionally between the inductors and the clock mesh, as opposed to clock trees where the charge flow is unidirectional.
3. Cyclos design utilities/scripts and RCM IP work in standard RTL/Verilog flows.
4. Coarse and fine dynamic frequency scaling is supported. Realize of course, as one reader pointed out, that the efficiency of the inductors/resonance falls off quickly with lower frequencies. The RCM will continue to operate but the power savings will be reduced at lower frequencies.
Thanks to all for your interest and again please feel free to contact me if you have any further questions or would rather comment in private.
Rakesh - There actually is very little affect on clock gaters. From the clock mesh and below, traditional clock tree synthesis tools are used for "localized" clock gating/routing. The benefits of the near-zero clock skew mesh, along with a much smaller tree to balance, makes the existing CTS methodology continued to be used.
Also, it is thus still possible to insert "useful skew" using CTS tools as many designers have been doing on past generation devices.
Resonant circuits reminds of Tesla, you should study what he achieved. With the possibility to integrate inductors on chip, you could put Tesla tech in micro scale in your chips. What does this mean ? Well, howabout a chip that powers itself once started. When you are running out-of-juice from your electric car, plug in your new handset and keep on driving. It gives all the juice you need. Impossible! you say. Not at all, this tech already exists but only on bigger scale. Google for Kapanadze free energy, he shows videos of devices with outputs from 5 kW to 100 kW.
Nice thing about resonant circuits is that higher the frequency the more power you get and smaller size is needed. Inductor's ability to induce power in another inductor depends on the speed of swithing (squared), voltage (squared), and amperage. With GHz speeds you can get lots and lots of more power compared kHz speeds. The trick you need to learn is to make output part so that it does not affect input. This is all explained in Tesla's patents. As you have already made resonant clock mesh, this nut should be easy to crack.
Frank - absolutely. As with any first time implementation of new technology, the approach was somewhat conservative. We believe savings as large as 20% are possible with more aggressive design and analysis.
Indeed, clock power is a large % of chip power. Most designers estimate the clock network consumes about 30-35% of overall power - so there is a significant advantage to implementing resonant clock meshes.
Regarding yield, designers using resonant clock meshes have actually realized no measurable yield degradation ... in some cases yields actually improve. Bear in mind that more than half of the typical clock tree drivers are eliminated with a resonant clock mesh - so there are many less candidates for circuit failure on chip. Consider that a clock buffer defect in a clock tree design makes the device unusable as an entire branch of the tree is no longer functioning. Not so with clock meshes - one buffer failure does not affect the function of the clock mesh as all buffer outputs are shorted together.
Granted, there can be a small area increase by adding the on-chip inductors which would reduce yield slightly ... but real world experience has shown that it's basically a wash - yield improvement or degradation is not expected. Most design teams today are quite happy to accept a small yield penalty in exchange for 10% total power reduction anyways.
More info can be found on the FAQ page of our website at www.cyclos-semi.com. Or feel free to contact me at email@example.com and I can provide very detailed technical info for you.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists from incubators join Peter Clarke in debate.