The one thing I've noticed missing from any discussion of the Tabula technology is the power efficiency. Based on the lack of discussion, the fact that the "3D" technique they are using means higher clock speeds and the fact that there seems to be a focus on high end networking applications... I'm guessing the power efficiency is less than traditional FPGAs? Though perhaps the reduced interconnect length combined with Intel's FINFETs would tip the scale in the other direction?
Perhaps something for EE Times to ask when next covering Tabula.
NASA's Orion Flight Software Production Systems Manager Darrel G. Raines joins Planet Analog Editor Steve Taranovich and Embedded.com Editor Max Maxfield to talk about embedded flight software used in Orion Spacecraft, part of NASA's Mars mission. Live radio show and live chat. Get your questions ready.
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