The future of low-power ICs will likely be based on integrated voltage regulators, probably starting with silicon interposers like these, but eventually right on the CMOS chip itself. On the way to that dream, though, there are a lot of weigh-stations, which we detailed in our latest feature story: "5 Ways to Reduce Power of Future ICs" which you can read here: http://bit.ly/AyRmLI
Guess that is why they have the voltage regulator in the lowest chip layer so that the thermal path for dumping heat is the shortest available.
I agree about the heat problem and also what always crosses my mind when I read about 3D ICs. Not so much solving the fabrication of TSV in an economic way, the wafer bonding part or getting proper models. It's of course interesting but more of a controllable engineering challenge than a show stopper.
Thermal heat dissipation, though. That's tricky and it will be interesting to see how it's solved in practise for the multilayer devices I've seen in powerpoint slides.
Inductors of that size mean very high switching
frequency and switching losses. Meanwhile an IC
technology's interconnect sheet resistance is bad
for overall conduction losses.
With FPGAs drawing .gt. 10A these days, you're
going to throw the same current that takes chip
scale pass FETs, through a skinny long winding?
Reliably and efficiently? Yeppers.
Can be done, OK. But it looks to require a lot of
"right customer expectations". Personally I find
the integrated ferrite & package approaches a lot
more sensible. The inductor is always the pig,
and that inductor doesn't look like it can
handle a whole lot of current or clock period.
For someone whose primary interest is the fact of
2.x-D integration, though, I'm sure it's all
@dick_freebird: very relevant points! I asked a question to the presenter on how they were intending to interconnect to the next level from either the Si interposers or the bottom chip in the stack when the current densities were crossing 1000A/Cm^2. I think there are going to be challenges in electro/stress-migration in Cu pillars or bumps that interconnect these, requiring a larger number -increased area & cost.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.