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re: Intel's Ivy Bridge delayed, says senior executive
yalanand   3/4/2012 11:50:27 AM
@Sylvie any particular reason for this delay ? Is it deliberate delay by Intel or is it really facing technical challenges at 22nm node?

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re: Intel's Ivy Bridge delayed, says senior executive
TarraTarra!   2/27/2012 8:04:46 PM
Why is it surprising? The new finfet technology is such a radical departure from previous tick-tock shrinks that some hiccup is to be expected. The very original timelines had Ivy Bridge introductions in Q4 11/Q1 12 timeframe, so that would amount to a glitch. Even the mighty Intel is not immune to the challenges of very deep submicron manufacturing. Note this is not a few working die to characterize for publications - this is shipping in volume with the yields that the business is based on - a big difference.

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re: Intel's Ivy Bridge delayed, says senior executive
chipmonk0   2/27/2012 7:35:02 PM
who are these reporters ? what are their qualification and track record for responsible journalism ?

the_floating_ gate
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re: Intel's Ivy Bridge delayed, says senior executive
the_floating_ gate   2/27/2012 4:29:23 PM
Jim McGregor of In-Stat told EE Times that according to his industry sources in Taiwan, Intel's Ivy Bridge server parts were only delayed from April 8 until April 29, though the dual core i5 and i7 parts for notebooks had been pushed out from a planned May 13th launch to June 3. Core i3 parts would launch as planned on June 24, said McGregor. That's three weeks - I am not sure a manufacturing glitch would fixable in 3 weeks considering cycletime is probably on the order of 10 to 12 weeks. Nobody knows - someone makes an assumption - this will be repeated and than it becomes "news" Why does not Sylvie digg up the interview or is there no written copy?

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re: Intel's Ivy Bridge delayed, says senior executive
resistion   2/27/2012 3:22:38 AM
They're waiting for people to clear out their current Sandy Bridge overstock, but everyone is waiting for Ivy Bridge, it's a vicious circle.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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