I think this move is also required to ease out the porting of the VIP adapters when working with hardware accelerators which is a weak link in the process.
I wrote relevant blog post on general VIPs @
JTAG VIP architecture is complaint with regular languages like C,C++,System C, System Verilog in conjunction with Methodologies like VMM,UVM,OVM etc. This is a industry standard and should be compliant without any issue.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.