I think this move is also required to ease out the porting of the VIP adapters when working with hardware accelerators which is a weak link in the process.
I wrote relevant blog post on general VIPs @
JTAG VIP architecture is complaint with regular languages like C,C++,System C, System Verilog in conjunction with Methodologies like VMM,UVM,OVM etc. This is a industry standard and should be compliant without any issue.
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