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Gaurav Jalan
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re: Synopsys introduces new VIP architecture
Gaurav Jalan   2/28/2012 1:11:02 PM
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I think this move is also required to ease out the porting of the VIP adapters when working with hardware accelerators which is a weak link in the process. I wrote relevant blog post on general VIPs @ http://whatisverification.blogspot.com

Neill.Mullinger
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re: Synopsys introduces new VIP architecture
Neill.Mullinger   2/28/2012 6:04:26 AM
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The debugging is not provided through a specific interface like JTAG; Each Discovery VIP generates the record of behavior seen on its protocol interface for display and debug in the Protocol Analyser.

MAVERICK230
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re: Synopsys introduces new VIP architecture
MAVERICK230   2/28/2012 5:53:42 AM
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JTAG VIP architecture is complaint with regular languages like C,C++,System C, System Verilog in conjunction with Methodologies like VMM,UVM,OVM etc. This is a industry standard and should be compliant without any issue.

Kinnar
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re: Synopsys introduces new VIP architecture
Kinnar   2/27/2012 7:26:10 PM
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Which interface VIP uses for the debugging purpose? Is it JTAG?



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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