I think this move is also required to ease out the porting of the VIP adapters when working with hardware accelerators which is a weak link in the process.
I wrote relevant blog post on general VIPs @
JTAG VIP architecture is complaint with regular languages like C,C++,System C, System Verilog in conjunction with Methodologies like VMM,UVM,OVM etc. This is a industry standard and should be compliant without any issue.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.