I think this move is also required to ease out the porting of the VIP adapters when working with hardware accelerators which is a weak link in the process.
I wrote relevant blog post on general VIPs @
JTAG VIP architecture is complaint with regular languages like C,C++,System C, System Verilog in conjunction with Methodologies like VMM,UVM,OVM etc. This is a industry standard and should be compliant without any issue.
Blog Doing Math in FPGAs Tom Burke 24 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...