it seems like the integration is in the package level, by combining at least 2 chips. This is not a breakthrough in the technology. More of an evolution that a revolution. But definitley this increased level of integration is welcome. We can use any increase in throughput and reduction in BER - it will open up new possibilities.
Nice idea to reduce signal integrity related problems and makes board designer's life easier. Although this could also have been achieved by placing the optical xceivers physically very close to the FPGA on the board to limit the length of the traces to less than half an inch.
I welcome the idea as this could be the beginning of technology trend of greater dependency on the programming logic going forward.
Altera has made it, this development might bring Altera forward in competition. This will make the FPGAs being widely used in the networking devices, where electronics will control the optics in native mode. In other words we can say "Electronically controlled Optics".
This is wonderful approach from Altera and Avago. Basic approach is to reduce design complexity and encourage many more designer to integrate high speed serial technology in many more products. I wish to see many application solved by this device.
I don't think this is either new or novel. I have seen this described about ten years ago. The problem has always been that the logic is in Silicon and the optical is in some other semiconductor. So they have to have I/O interconnect which adds parasitic capacitance and inductance degrading high speed signals. They may have reduced this by using bumped die packaging rather than bond wires, but I don't think they have really broken new ground.
Did anyone notice the speed vs. error rate? 10^11 bits per second data rate and better than 10^-12 error rate. That means nearly an error every 10 seconds. I assume this would be handled by a good protocol, but it seems like maybe we need to bump up the requirements for such fast interconnect.
With regard to Xilinx -- I can;t speak for them and I have no advanced knowledge -- but take a look at their 2.5D FPGAs in which four FPGA die are mounted on a silicon interposer in the same package -- and the silicon interposer provides around 10,000 silicon-speed connections between each adjacent pair of FPGA die .... now suppose you replace one of the FPGA die with an optical interconnect subsystem...
All good questions. Let's look at it this way -- in 1000 years do you think we will still be using silicon-based chips with copper interconnect on our PCBs ... how about 100 years?
If we come closer to home, I bet that in 10 years a lot of the higher-end chips and subsystems (microprocessors, memory, etc) will be using optical interconnect.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.