As I wrote in May, ST-E reckons that w/FD-SOI's power savings, they can add a full extra day for smartphone users (see http://www.advancedsubstratenews.com/2012/05/novathor-smartphone-chip-on-28nm-fd-soi-st-ericsson-blogger-tells-all-pc-mag-sees-light/), which is huge.
And IBS says that even counting the cost of the wafer, per-die FD-SOI comes in at about *half* the cost of bulk (planar and/or FinFET) at 20nm (which ST has in very-fast-follow), because it saves process steps -- see http://www.advancedsubstratenews.com/2012/11/ibs-study-concludes-fd-soi-most-cost-effective-technology-choice-at-28nm-and-20nm/
I believe that ST-Erikson are willing to pay extra for their wafers in order to reap the 40 percent savings in battery power, which mitigates the risk. The other guys are just validating that they can get the higher performance, and by the time they get to volume production, the price may have gone down due to high demand. Of course, bulk silicon will always be cheaper for the raw wafers.
Blog Make a Frequency Plan Tom Burke 17 comments When designing a printed circuit board, you should develop a frequency plan, something that can be easily overlooked. A frequency plan should be one of your first steps ...