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Swapnajit.Mitra
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re: Viewpoint: Towards a lean and mean SystemVerilog
Swapnajit.Mitra   4/2/2012 7:58:16 PM
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Thanks Dennis and others for giving inputs to the thread. I was attached to the development process for SystemVerilog, so my opinion may be biased. Nonetheless, as the author of this article, I felt I might as well throw in my 2 cents in response to Dennis’ questions. Overall, I think there are 3 different topics: 1) Should we eliminate PLA system calls from a combined Verilog and SystemVerilog? My response to this is obvious from this article. I have not seen anyone cheering to keep them as they are. I am assuming we all concur that no tear will ever be shed if they disappear. 2) Should we look into the SystemVerilog LRM for all redundant/duplicated/competing features and scrutinize them for possible elimination? My answer is - once again should be obvious from the article - Yes. I never heard anyone arguing in favor of keeping anything that is redundant/duplicated/competing/inefficient or something that makes the overall language cumbersome. I would assume everyone concurs on this as well. 3) Should we throw away SystemVerilog all together and start from anew? Although it may seem like just the other day, SystemVerilog has been around now for about 10 years in real code that verified real system. Just as in any other language, SystemVerilog may have flaws and any such flaw needs to be corrected. But rejecting SystemVerilog all together will amount to throwing the baby with bath water and will negate the investments made by all concerned - users in building their knowledge, companies who developed their products using it and of course the EDA companies. Or, in other words, I do not see disagreement here either. In light of the above agreements, if I may re-state the 'Call to Action' part one more time: (a) Accept the fact that SystemVerilog still needs to go through growing pain, continuously cleaning up any flaw it may have, (b) Contribute to the above process by participating in standard activities, (c) Use SystemVerilog in all of your projects.

DKC
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re: Viewpoint: Towards a lean and mean SystemVerilog
DKC   3/20/2012 4:43:59 AM
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This is reminding me of Stuart Swan's claim the other day at his IEEE talk that the "language wars" were over. It would be true if they all worked properly, but they don't. VHDL is particularly bad with respect to simulation semantics - i.e. it's crap for modeling. Verilog-AMS which is key to modeling analog things - like power-management - has not been integrated with either of these "titans", so I expect things will get worse before they get better. SystemVerilog is an unholy mess, and I voted that it shouldn't go to the IEEE before being cleaned up. Recent SV additions for discrete analog modeling are completely dysfunctional - and were done deliberately ignoring existing Verilog-AMS approaches. Is there a fix? - definitely, but I don't think there is enough space here to get into that, and I can think of some people that won't like it.

Dennis.Brophy
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re: Viewpoint: Towards a lean and mean SystemVerilog
Dennis.Brophy   3/19/2012 11:17:22 PM
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Swapnajit, This reminds me of the "first 'shot over the bow' in the VHDL 1998 wars" by Krolikoski, Levia & Ussery of Cadence. (http://www.it.uc3m.es/~ifip/chdl97/tut-mb.html) The war never happened. At the time the "trimming" was suggested the team I was a member of was in the market with a rather full implementation. While there may be a few who have to know all or ever will know all of SystemVerilog, the specializations by many allow a subset of it to be used to make the task of designing and verifying something that can be accomplished. I am open to hear what others think would be a good alternate to what exists today. Should we start from scratch with something new? Or should we just remove that which no longer represents the state-of-the-art, like the PLA system tasks? -Dennis

Swapnajit.Mitra
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re: Viewpoint: Towards a lean and mean SystemVerilog
Swapnajit.Mitra   3/16/2012 6:54:57 PM
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To answer your question 'if there is no longer a need for PLA system tasks why would anyone bother to implement a replacement in SV?' This is the line from the above article: '...these system tasks should be deprecated from the language. If they are, a migration path for the users of these system tasks should be provided.' The users of these tasks are small but not zero.

dyson_
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re: Viewpoint: Towards a lean and mean SystemVerilog
dyson_   3/16/2012 9:18:53 AM
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Nice idea to thin down Verilog/SV but your case study sort of contradicts itself. If there is no longer a need for PLA system tasks why would anyone bother to implement a replacement in SV? Maybe Verilog/SV has become the COLBOL of the EDA world? BTW if they count "begin" and "end" as Verilog keywords, then { and } should be counted as such in C/Java ;-)

defendor
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re: Viewpoint: Towards a lean and mean SystemVerilog
defendor   3/15/2012 6:59:38 AM
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here's a better idea. Allow users to send reference pointers to other modules over verilog input/output ports. this would solve all of the OVM/TLM nonesense. example: module sequencer( input module fiber ); initial begin fiber.push(x); fiber.pop(y); end endmodule; module fifo( output module fiber ); assign fiber = thismodule; task push; endtask task pop; endtask; endmodule; Receiving module can receive

DKC
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re: Viewpoint: Towards a lean and mean SystemVerilog
DKC   3/14/2012 5:21:17 AM
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Towards a lean and mean SystemVerilog? It has been on the bloat path since its inception, I can't see them cleaning it up now. http://parallel.cc



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