The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm.
The FinFET is NOT planar - by going FinFET Intel actually accelerated Moore' law.
There is Moore law
and there is capital intensity which is increasing.
Now it's becoming more and more about fix cost absorption:
a fast, clean ramp will become super crucial/ mandatory.
Here's Intels litho roadmap
Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display.
Apple's A5X uses the same 45nm process used on the original Ipad - one difference is that the A5X chip is 3x the size compared to the original A4 - talking about cost per gate....
IOW that means they need 3 x wafers to get the same number of dies - what a business model
The problem is that the semiconductor business model has been broken for many years now. The end of Moores law makes it even worse for large leading edge manufactures and equipment vendors as return on investment shrinks with each new process node.
The easy shrinks of silicon have already been done. As it gets harder for each next step, eventually we all knew that it would become less economical to make that step than to stay where we are. We may be at that point, but there will still be innovation that will create cost savings as we go forward. It just may not be as dramatic.
I would remind only some layers would be effectively doubled, e.g. gate, active, metal1, contact. If you're only adding 10% more layers, but shrinking to 60% area, you're still cost-effective, just less so than previous node shrinks.
Yes, the reality is very clear. The cost for 0.7x next generation scaling is escalating too scary numbers for all aspects:Fab cost,process R&D,EDA and libraries,Chip design,mask set,...
But that is not the only option to continue advance semiconductor devices. We can keep Moore's Law using the recent breakthrough of monolithic 3D http://www.monolithic3d.com. Clearly most of the NAND vendors already going to that direction.
I'm glad someone is finally laying this all out publicly.
A decade ago, Gordon Moore told me his "Law" would slow down before we hit the end as we approached the size of silicon atoms. Well, we're seeing the slow down, Mr. Moore.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.