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the_floating_ gate
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re: Feature dimension reduction slowdown
the_floating_ gate   3/22/2012 5:49:55 AM
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The recent scanner problems on the 28-nm line indicate that the limits of many technologies are being reached. What scanner problems - please explain

the_floating_ gate
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re: Feature dimension reduction slowdown
the_floating_ gate   3/22/2012 5:11:12 AM
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The 22-nm FinFET high-volume ramp-up is already more than two years behind 32-nm. The FinFET is NOT planar - by going FinFET Intel actually accelerated Moore' law. There is Moore law and there is capital intensity which is increasing. Now it's becoming more and more about fix cost absorption: a fast, clean ramp will become super crucial/ mandatory. Here's Intels litho roadmap http://www.electroiq.com/articles/sst/2012/02/spie-advanced-lithography-intel-tsmc-tool-roadmap-takeaways.html Apple has already adjusted in that the only real enhancement to the iPad from a hardware perspective is higher-resolution display. That's rediculous: Apple's A5X uses the same 45nm process used on the original Ipad - one difference is that the A5X chip is 3x the size compared to the original A4 - talking about cost per gate.... IOW that means they need 3 x wafers to get the same number of dies - what a business model

any1
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re: Feature dimension reduction slowdown
any1   3/21/2012 12:57:21 PM
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The problem is that the semiconductor business model has been broken for many years now. The end of Moores law makes it even worse for large leading edge manufactures and equipment vendors as return on investment shrinks with each new process node.

daleste
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re: Feature dimension reduction slowdown
daleste   3/21/2012 1:39:23 AM
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The easy shrinks of silicon have already been done. As it gets harder for each next step, eventually we all knew that it would become less economical to make that step than to stay where we are. We may be at that point, but there will still be innovation that will create cost savings as we go forward. It just may not be as dramatic.

resistion
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re: Feature dimension reduction slowdown
resistion   3/20/2012 3:11:15 PM
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I would remind only some layers would be effectively doubled, e.g. gate, active, metal1, contact. If you're only adding 10% more layers, but shrinking to 60% area, you're still cost-effective, just less so than previous node shrinks.

Or_Bach
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re: Feature dimension reduction slowdown
Or_Bach   3/20/2012 7:59:50 AM
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Yes, the reality is very clear. The cost for 0.7x next generation scaling is escalating too scary numbers for all aspects:Fab cost,process R&D,EDA and libraries,Chip design,mask set,... But that is not the only option to continue advance semiconductor devices. We can keep Moore's Law using the recent breakthrough of monolithic 3D http://www.monolithic3d.com. Clearly most of the NAND vendors already going to that direction.

rick merritt
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re: Feature dimension reduction slowdown
rick merritt   3/20/2012 6:17:40 AM
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I'm glad someone is finally laying this all out publicly. A decade ago, Gordon Moore told me his "Law" would slow down before we hit the end as we approached the size of silicon atoms. Well, we're seeing the slow down, Mr. Moore.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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