The yield equation requires one to supply die area, defect density, and the magic "process complexity factor". You only have one of those three numbers.
The yield model that is ultimately chosen will be the one that best correlates with measured yield.
80% yield means 250,000*226*80% = 53M units. first of all, the dies size of 263mm2 could not have 80% according to bose-einstein yeild/defect density equation for 32nm. Second of all, AMD is only shipping 1M-1.5M units of Llano per month. So if the yield is so good as 80%, GF won't ship that many wafers. AMD only needs 5-10,000 w per month. 10,000*263*80% = 2M.
80% yield may be referred to wafer yield but not the parametric yield. The difference is more than 20% based on the product roll-out. Actually, TSMC has learned how to do a good job for 28nm process to ensure that the products goes for volume production within short period of time.
Actually, GF said yields for 32nm SOI are now over 80%, and they're beating TSMC. So SOI took a bad rap for low yields in the beginning -- but should we be asking if it was really the learning process for their version of HKMG that caused delays? Their 32nm HKMG SOI was a major technological achievement -- but being first out of the gate, did they not run into a wall of unrealistic expectations from the bean counters? Hmmm.
It's simple math why 250,000 wafers shipment is not such a rosy picture. In fact this is a bad picture for foundry. Here is why. The die size of Llano is around 228mm2 and you get 263 gross dies per 12" wafer. The total gross dies = 250,000*263 = 66M units. So how many Llano AMD shipped so far? Probably less than 10M + some in inventory. That mean the wafer yield on 32nm SOI process is really low 10-20%. This means GF is losing thousands of $ every wafer they shipped. This is exactly why AMD had to go to TSMC for 28/20nm. The yield on 32nm could go up eventually but it took too long for AMD to get the manufacturing going in volume and GF likely will repeat this scenario all over again for 28nm and 20nm and so on.... I would stay away from GF until they prove themselves that they can manage manufacturing repetability for advanced nodes.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.