@sharps_eng: yes, you are right about the thermal challenges in the stack and this will have some limitations on the logic die. The hybrid memory cube site claims the memory cube will consume 70% less energy per bit than DDR3 DRAM memories but will deliver 15x the performance. This remains to be seen.
Aren't these things going to get pretty hot with certain patterns of usage and data?
For instance if the access pattern does not allow the stacked devices time to cool off between bursts? The internal layers are short on cooling opportunities that's for sure.
Perhaps they can rely on certain friendly usage patterns, with particular cache controllers and DMA engines in specific architectures etc.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.