I think there is a hidden extra cost coming down the line just from the fact that three different solutions are being tooled in parallel since no one knows which will make it. All of these approaches are expensive by themselves. Having to hedge your bets by tooling all three is very costly and the foundries will have to recoupe that cost some how.
There was a lot more going on at ISPD that I could not include in the story, but you might want to check out on their webiste:
Here are a few highlights: Three talks were given professor Liuís former students--Jason Cong, a chancellorís professor and director of the Center for Customizable Domain-Specific Computing of UCLA, spoke on how Liu "Transformed Ad Hoc EDA to Algorithmic EDA." Professor Martin D. F. Wong at University of Illinois (Urbana-Champaign) spoke on how Liu applied simulated annealing to re-shape the EDA landscape. And Synopsys Fellow Tong Gao and his colleague Prashant Saxena spoke on Liu's visionary intuition in the identification and†formulation of several issues in routing, interconnect crosstalk optimization and performance-aware layer assignment that subseaquently had wide influence over the semiconductor and EDA industries.
There was also the annual contest, this year on discrete gate sizing, organized by an Intel team led by research scientist Mustafa Ozdal at Intel Strategic CAD Labs. 32 academic and industrial teams from four different continents entered the contest with 18 teams making it through to the submissions phase. The winner was team from National Taiwan University led by professpr Yao-Wen Chang and his graduate students Kuan-Hsien Ho, Po-Ya Hsu, and Yu-Chen Chen. Second plance went to a team from Universidade Federal do Rio Grande do Sul, Brazil, led by professor Marcelo Johann. And third place went to a joint team of National Tsing-Hua University and Missouri University of Science and Technology led by professors Yiyu Shi and Shih-Chieh Chang.