Lets continue and detail that the 3D-IC space has two main type. The TSV base and the monolithic 3D. The TSV is in most cases stacking of wafer process independently, than one wafer is thin to about 50 micron and stack as a die or a wafer on top of another wafer, and than connected using TSV that are about 5 micron. While monolithic 3D will be about a fabricating additional layer of semiconductor of 100nm on top of previous processed wafer and continue the processing of transistors and interconnects. The monolithic 3D would provide 10,000x higher vertical connections than TSV. We can find more information on some monolithic 3D flow in http://www.monolithic3d.com
Great piece, Max. I think this is truly a fascinating technology that can certainly benefit by more tutorial information like you have provided. In fact, it seems that above and beyond how it differs from SiP and MCMs, a lot of folks seem to get 2.5D and 3D IC stacking confused with what was traditionally called finfet technology but has been recently rebranded seemingly be Intel as "tri-gate" or "multigate" transistor technology. This of course could get even more confusing if and when folks actually start doing 3D stacking with finfet based devices.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.