Great piece, Max. I think this is truly a fascinating technology that can certainly benefit by more tutorial information like you have provided. In fact, it seems that above and beyond how it differs from SiP and MCMs, a lot of folks seem to get 2.5D and 3D IC stacking confused with what was traditionally called finfet technology but has been recently rebranded seemingly be Intel as "tri-gate" or "multigate" transistor technology. This of course could get even more confusing if and when folks actually start doing 3D stacking with finfet based devices.
One thing I would like, that you would probably do very well Max, is something on how FPGAs are programmed, say from a specific application idea through the verilog/VHDL (not sure if that's right) to the actual programming. Next time you have a spare sunday (or three...)???
PS Max I put FPGA fundamentals into the search box of the EETimes home page and I see you did something on this in 2008...however I get 404 errors on all of the links. Maybe you could resurrect that as a starting point? Not sure if I have seen it before...
PPS. Must have mis-spelt something, your Fundamentals of FPGAs is here
And very good it is too, almost exactly what I asked for. So you can have the next 3 sundays off....
Lets continue and detail that the 3D-IC space has two main type. The TSV base and the monolithic 3D. The TSV is in most cases stacking of wafer process independently, than one wafer is thin to about 50 micron and stack as a die or a wafer on top of another wafer, and than connected using TSV that are about 5 micron. While monolithic 3D will be about a fabricating additional layer of semiconductor of 100nm on top of previous processed wafer and continue the processing of transistors and interconnects. The monolithic 3D would provide 10,000x higher vertical connections than TSV. We can find more information on some monolithic 3D flow in http://www.monolithic3d.com
Max, very good mythbusting material.
I recall that National Semi had stacked ICs for the NSC800, a Z-80 clone. You could simply plug RAM chips, eeprom, and a peripherals chip on top of the processor, to have a full computer on the DIP-40-pin socket of the processor.
It could be called a "paleo-3D" technology [grin].
Thank you so much for your kind words -- I was worried about putting some of the simple stuff in, but for myself when I'm reading something by someone else, I always like to get the history and suchlike...
Great job! As mentioned above, monolithic 3D deserves to be added. A similar job on various memory technologies: volatile (SRAM, S/DRAM etc.), non-volatile (E/E/PROM, NAND/NOR Flash etc.) would be very nice.... when you have time, no pressure (grin)
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.