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Kinnar
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re: Analysts start Intel Ivy Bridge CPU teardown
Kinnar   4/16/2012 11:34:36 AM
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Intel has gone a way beyond the other are trying, that too with a new 3D connections technique, this will let then achieve the power saving standards compared to their immediate rivals. UBM's initiative lets the world know about what actually is happening inside the chips.

elctrnx_lyf
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re: Analysts start Intel Ivy Bridge CPU teardown
elctrnx_lyf   4/16/2012 8:23:57 AM
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Why does UBM wants to do this tear down of the chip? Will this information be useful for any other manufacturers. Anyways I would like to read the complete report if I get a chance.

resistion
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re: Analysts start Intel Ivy Bridge CPU teardown
resistion   4/13/2012 12:40:48 AM
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If you look at the gates and diffusion contacts together, it really does look like a 20-22 nm half-pitch that is double-patterned.

KarlFredrik
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re: Analysts start Intel Ivy Bridge CPU teardown
KarlFredrik   4/12/2012 12:50:45 PM
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As far as I know, Intel is still using ordinary wafers, which implies a 4-terminal device. FD-SOI is 3-terminal and I guess that's coming sooner or later (SOITEC ftw!).

US Made
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re: Analysts start Intel Ivy Bridge CPU teardown
US Made   4/12/2012 12:16:42 AM
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Can you pls. comment on if these are 3 terminal or 4 terminal FinFets



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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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