sorry, in my annoyance at the PDF, I forgot to mention that the Series is a favorite of mine, absolutely a wealth of quality information that is hard or impossible to find or know without the experience you clearly have. I am continually learning from you, thanks, but just hate the PDF :)
Why is the full linked list of all tips in the series a PDF file??? I can't even use that on some of my mobile devices, but I can read the articles.
The absurdity of a PDF file is clear when you see that for the next tip you have to change it, and I have to re-download it (or if I get busy and miss a few, I come back want to catch up, I need to download a PDF)
Why isn't that just a link to a home page for the Power Tips Series on eetimes.com ? On that home page is the hyperlinks to other articles in the series.
Some Drivers Do have Programmable Dead time to prevent shoot-through. How ever this limits the usable duty cycle range.
Robert has considered 12:1 buck reg, which is one of the difficult examples. This timing problem becomes more important when we need to achive duty cycles down to 1%
The timing of the upper switch turn-on is helped by a few factors. For example, as we can see in Robert's figure 1C, the gate voltage is at a low level anyhow if the upper switch turns on too early. This limits the possible amount of shoot-through. More importantly, both Spice and O-scope plots have showed me that the parasitic source inductance plays a critical role in lowering shoot-through. High di/dt across Ls in the lower switch "pushes" the gate voltage higher even though the G-S voltage is falling, and is often mistaken for a Miller plateau. The upward rise in V-gate in figure 1A is this very effect. Remember: Vgate is not the same as Vgate-source.
D. Hambley, SENTEK Engineering
There is no single schematic here to show, it depends on what you are driving--the point here is to show you what you need to be aware of when doing a circuit. It's not a "cookbook" situation, unfortunately.
For synchronous buck topology I have used of the shelf PWM chips, which usually have built in optimization of ON/OFF timing between the hi-side and lo-side switches...not much to do with manual tuning.
Can I add that designers do not have an easy way to time the gate drive in a reliable, low-cost circuit. No one device or circuit has appeared that fixes this problem at the right price and reliability point. I have seen many circuits loaded with hand-tweaked RC networks.
If you read carefully you can spot that this article is talking about a buck converter, but using terms like hi-side and lo-side which are normally associated with H-bridges. In H-bridges, timing is a symmetric problem and turning on the lo-side is equally critical.
The synchronous FET pair in this buck converter can also easily have such a symmetric mode, depending on the design parameters.
A brief and important analysis about the low side and high side FET when used as a switch.This is used in many applications including electronic ballasts. This analysis to be included in the R&D labs libraries.Also usable to reduce the radiations and go for EMI certification.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.