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the_floating_ gate
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
the_floating_ gate   4/16/2012 11:29:27 PM
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Mark Bohr addresses SOI versus bulk One on One with M. Bohr http://semimd.com/blog/2011/07/14/one-on-one-with-mark-bohr/

krisi
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CEO
re: Silicon-on-insulator at ST and IBM closing gap with Intel
krisi   4/16/2012 10:03:27 PM
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I thought people gave up on SOI back in 2011 (there was an EE Times on this topic announcing SOI death)...who resurrected SOI and why? Kris

SiliconAsia
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
SiliconAsia   4/16/2012 9:32:55 PM
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That's exactly the point! Do foundry customers want these or is IBM just pursuing these for the sake of demonstrating technological prowess?

R_Colin_Johnson
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Blogger
re: Silicon-on-insulator at ST and IBM closing gap with Intel
R_Colin_Johnson   4/16/2012 9:19:30 PM
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I believe that Intel would agree with you. And you may be right about foundries as well, except for one fact. Namely, that if foundry customers say they want to use SOI wafers, then foundries will let them. Period.

R_Colin_Johnson
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Blogger
re: Silicon-on-insulator at ST and IBM closing gap with Intel
R_Colin_Johnson   4/16/2012 9:17:30 PM
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Solitec is not the only supplier of SOI wafers. In fact, nearly any wafer maker can be pursuaded to create functionalized wafes for special purposes--especially at the 400 percent premium they can charge!

SiliconAsia
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
SiliconAsia   4/16/2012 9:06:01 PM
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IBM continues to make impacts on technological progress(es) and what they are doing has R&D value and it contributes to the evolution of foundry process(es). But at the end, Foundries may not use these processes as a baseline processes for their customers. Simply it may not be THE process(es) foundries can use for baseline process economically.

the_floating_ gate
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re: Silicon-on-insulator at ST and IBM closing gap with Intel
the_floating_ gate   4/16/2012 7:40:51 PM
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When it came to copper IBM said SilK was the way to go... when it came to sub 4X IBM said gate first was the way to go... Would Soitec be able to supply sufficient wafers (eventually @ 450mm) ?

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