Although, Intel did gain a lot of ferroelectric memory knowledge in their research with Thin Film Electronics a few years back.
But I agree there is no sign they are using that knowledge directly in these NAND flash memories.
The conventional wisdom is for companies to go to vertically stacked NAND memory cells thus keeping the same planar geometry (and electrons per bit) while getting greater memory denistry per die area.
Thanks resistion, I think I see now. The high-k dielectric's polarization isn't used as a memory element at all.
Is it correct to think of it as simply providing a capacitance threshold that's used as the limit on current flow?
If I'm reading this correctly, Intel/MU say they have started "volume production" of a ferroelectric NAND device; that others (such as a group from AIST, see below) have been working on similar IP but are far behind because they are focused on (a) a different ferroelectric material as compared to the gate material Intel has developed, and (b) a more complicated FinFet structure rather the "old school" planar circuit design developed by MU.
see AIST work disclosed at:
(2008 cell demonstration)
(2012 64Kb cell array demonstration)
I find this all very very very difficult to believe in view of the industry's track record of premature claims of new NV memory "production;" but most of all because Intel/MU are claiming to be able to produce this planar "Fe-NAND" device at sub 30nm lithographies currently with plans to soon drop production below the 20nm node. Such devices with even half the performance claimed for the AIST cell design would go through the current FLASH application markets like something through a goose.
Has Intel/MU developed a new memory IP or just a new promotion? Have they ever submitted anything at an industry conference on such IP?
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists from incubators join Peter Clarke in debate.