There is an underlying assumption in this discussion that the cost of an EUV tool that could meet 100WPH would actually be lower cost than a triple patterning immersion solution. Especially when you add in the potential need to regularly replace EUV masks due to defects that occur without a pellicle to protect them. What would be the reaction if after they finally get it working it costs more than multi-patterning methods?
Logic needs defect-free EUV, which means inspection tools ASML has no influence over. DRAM has billions of contacts which each require a noisier level of EUV photons, so they will require dose to increase for higher resolution. ASML has done all it could under its control, no one will fault it for giving up EUV. Unless it won its immersion orders by promising EUV.
My understanding is that Intel has already frozen their 14 nm design rules so EUV will not be Intel's litho tool of choice at 14 nm. Since the biggest ship (Intel) has already sailed and the IBM fab club and TSMC must be close behind them who does that leave? I think ASML is just now admitting what has been apparent for several months, that EUV will miss yet another major node.
Blog Doing Math in FPGAs Tom Burke 13 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...