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any1
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re: DRAM, foundry logic in race to use EUV, says ASML
any1   4/19/2012 1:05:38 PM
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My understanding is that Intel has already frozen their 14 nm design rules so EUV will not be Intel's litho tool of choice at 14 nm. Since the biggest ship (Intel) has already sailed and the IBM fab club and TSMC must be close behind them who does that leave? I think ASML is just now admitting what has been apparent for several months, that EUV will miss yet another major node.

resistion
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re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/19/2012 1:58:37 PM
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Logic needs defect-free EUV, which means inspection tools ASML has no influence over. DRAM has billions of contacts which each require a noisier level of EUV photons, so they will require dose to increase for higher resolution. ASML has done all it could under its control, no one will fault it for giving up EUV. Unless it won its immersion orders by promising EUV.

resistion
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re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/19/2012 2:03:54 PM
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Actually has the same noise problem as DRAM. ASML better focus on faster immersion tools.

resistion
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CEO
re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/19/2012 2:05:01 PM
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Logic has the same noise problem as DRAM.

PV-Geek
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re: DRAM, foundry logic in race to use EUV, says ASML
PV-Geek   4/20/2012 12:52:49 AM
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There is an underlying assumption in this discussion that the cost of an EUV tool that could meet 100WPH would actually be lower cost than a triple patterning immersion solution. Especially when you add in the potential need to regularly replace EUV masks due to defects that occur without a pellicle to protect them. What would be the reaction if after they finally get it working it costs more than multi-patterning methods?

double-o-nothing
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re: DRAM, foundry logic in race to use EUV, says ASML
double-o-nothing   4/20/2012 1:35:26 AM
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If 14 or 10 nm is expected to be the "last" node for practical purposes, there won't be any opportunity for next-generation litho insertion.

KB3001
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CEO
re: DRAM, foundry logic in race to use EUV, says ASML
KB3001   4/22/2012 1:08:50 PM
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Is not it inevitable that EUV will eventually win at some lower process node?

resistion
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CEO
re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/22/2012 3:23:49 PM
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I think now a problem is EUV cannot be superior for more than one or two nodes over the existing lithography. That may not be enough to justify. Also the issues are not monitored completely enough. Besides source power, how about defects, LER?

Diogenes53
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re: DRAM, foundry logic in race to use EUV, says ASML
Diogenes53   4/26/2012 1:36:43 AM
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Thank goodness the "race" to EUV, which started as a sprint (coming at 65nm), has "ended" in a marathon (1nm?). Sadly, for those users who invested their careers in EUV, it is more like SETI, the endless search for extraterrestrial life. It may happen, but not likely in our lifetime. Does Mr. Meurice care? Of course not. EUV/SXPL (yes, fans, it is STILL x-ray). As long as he can sell 2 immersion tools without meaningful competition, EUV remains a shell game.

Diogenes53
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Rookie
re: DRAM, foundry logic in race to use EUV, says ASML
Diogenes53   4/26/2012 1:41:06 AM
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So it was believed at 65, 45, 32, 22, 14, and, now, 10nm. Inevitable at each node. Definition:unable to be avoided, evaded, or escaped; certain; necessary: an inevitable conclusion. 2. sure to occur, happen, or come; unalterable: The inevitable end of human life is death. Particularly as regards #2, is EUV as "inevitable" as death? If so, I now feel immortal!

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