Breaking News
Comments
Newest First | Oldest First | Threaded View
<<   <   Page 2 / 2
double-o-nothing
User Rank
Rookie
re: DRAM, foundry logic in race to use EUV, says ASML
double-o-nothing   4/20/2012 1:35:26 AM
NO RATINGS
If 14 or 10 nm is expected to be the "last" node for practical purposes, there won't be any opportunity for next-generation litho insertion.

PV-Geek
User Rank
Rookie
re: DRAM, foundry logic in race to use EUV, says ASML
PV-Geek   4/20/2012 12:52:49 AM
NO RATINGS
There is an underlying assumption in this discussion that the cost of an EUV tool that could meet 100WPH would actually be lower cost than a triple patterning immersion solution. Especially when you add in the potential need to regularly replace EUV masks due to defects that occur without a pellicle to protect them. What would be the reaction if after they finally get it working it costs more than multi-patterning methods?

resistion
User Rank
CEO
re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/19/2012 2:05:01 PM
NO RATINGS
Logic has the same noise problem as DRAM.

resistion
User Rank
CEO
re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/19/2012 2:03:54 PM
NO RATINGS
Actually has the same noise problem as DRAM. ASML better focus on faster immersion tools.

resistion
User Rank
CEO
re: DRAM, foundry logic in race to use EUV, says ASML
resistion   4/19/2012 1:58:37 PM
NO RATINGS
Logic needs defect-free EUV, which means inspection tools ASML has no influence over. DRAM has billions of contacts which each require a noisier level of EUV photons, so they will require dose to increase for higher resolution. ASML has done all it could under its control, no one will fault it for giving up EUV. Unless it won its immersion orders by promising EUV.

any1
User Rank
CEO
re: DRAM, foundry logic in race to use EUV, says ASML
any1   4/19/2012 1:05:38 PM
NO RATINGS
My understanding is that Intel has already frozen their 14 nm design rules so EUV will not be Intel's litho tool of choice at 14 nm. Since the biggest ship (Intel) has already sailed and the IBM fab club and TSMC must be close behind them who does that leave? I think ASML is just now admitting what has been apparent for several months, that EUV will miss yet another major node.

<<   <   Page 2 / 2


Most Recent Comments
eetcowie
 
eetcowie
 
eetcowie
 
David Ashton
 
eetcowie
 
David Ashton
 
eetcowie
 
eetcowie
 
eetcowie
Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Saddleback Sale – It's Happy Dance Time
Max Maxfield
Post a comment
It's no secret that I'm a huge fan of the products from Saddleback Leather. As I sit here at my desk, I'm wearing one of their 1¾" wide Tow Belts, upon which rests one of their Belt ...

Engineering Investigations

Air Conditioner Falls From Window, Still Works
Engineering Investigations
Post a comment
It's autumn in New England. The leaves are turning to red, orange, and gold, my roses are in their second bloom, and it's time to remove the air conditioner from the window. On September ...

David Blaza

The Other Tesla
David Blaza
5 comments
I find myself going to Kickstarter and Indiegogo on a regular basis these days because they have become real innovation marketplaces. As far as I'm concerned, this is where a lot of cool ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
47 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...