Having managed ASIC designs for several years I doubt whether this new design technology can replace what tens or hundreds of designers per project are currently doing...sounds too good to be true...maybe for simple designs with far from optimum implementation...but if I am wrong these guys will swallow Cadence, Synopsys and Mentor in one scoop ;-)...Kris
This sounds like a quick & dirty "disposable" mask data substitute for a traditional design house for those who don't have a vested interest in mask data maintenance and re-use. Unless these magical super-secret tools are eventually released into the wild, I don't see this approach getting very popular. Although it sounds impressive in theory, I think the real world will get in the way of their success. The design process is fundamentally iterative in nature, and anything designed using a linear approach is almost guaranteed to come up short.
If they really have achieved what they claim, that is to take a C algo to GDSII in a few weeks, with comparable power/area as of traditional RTL design, then thats really awesome. However many companies have made similar claims in the past and failed pathetically in the market, which makes me a bit skeptical.
Thanks for your interpretation Dr Trevorkian. I didn't check their website, just read the article, and my skepticism was raised by several comments including "suite of software tools that interprets a customers' C-code without their having any knowledge of Algotochp's proprietary technology and tools."
So I interpreted it the same way you did, as a sort of consulting agreement, with the added twist of "we have some proprietary tools that we can't let customers have access to, but our guys know how to run them."
I should think a potential customer would be more comfortable if they just said they have a customizable VLIW or whatever it is, and proprietary tools to match, and that they also have in-house implementation experts and licenses for the usual IC implementation tools -- Synopsys, Cadence, Mentor, etc. -- because nobody in their right mind is going to sign off on a tapeout of some GDSII generated by a proprietary tool, with STA, DRC, LVS, power analysis & IR drop analysis, etc. also performed by a proprietary tool.
A few things.
First off, this is not being sold as a tool. You send your C-algorithm along with some specifications (see below for an excerpt from their webiste), and then you are sent back a GDSII targeted for a particular Foundary + process, 8-16 weeks later. This is more of an accelerated consulting agreement. I agree with Frank that having an RTL netlist as well would be more useful.
Second, the figure in this article makes it clear that there is a particular architecture with a customized DSP, microcontroller, and peripherals. It isn't clear what the level of customization here is. This could range from very sophisticated program analysis mixed with behavioral synthesis and HW/SW partitioning to a template architecture which is hand-tweaked for the given application.
Finally, without more information it's unclear what the real approach is and how legitimate it is without more information. All of this said, very interesting.
--- Quoting their website at: http://www.algotochip.com/about.html
The following are the required information from the customer:
C-Code for the algorithm (Fully support ANSI C and no changes required to customers C-Code)
Test-Vectors to check the C-Code
Desired Fabrication House and Process
Desired Standard Library and Memory Compilers
Real-Time performance constraints
Target Area and Power
Testability Features (scan, bist etc)
C code in and GDSII out? So we are to believe that in addition to a front end tool that analyzes the C code and does hardware-software partitioning and architecture optimization, they also have a synthesis engine, a place & route engine and a static timing analysis engine? One tool that replaces the entire tool chain for IC design?
Something said in the article sounds suspicious: "The resultant GDSII design, from which an EDA system can produce the file that goes to TSMC..."
What "EDA system" and why? If this new tool outputs GDSII, then you're done -- unless the GDSII has DRC violations, or the underlying design has timing violations, etc. If the GDSII that is output by this tool isn't 100% ready for TSMC, they why do they bother generating it? A netlist that is ready for P&R would be a lot more useful than a GDSII file that is not quite ready for manufacturing.
All you C-programmers out there unite! Now all you need to do is describe your application by a C program, plus a set of test stimulus vectors, and this startup can give you an foundry-ready SoC design in just a few weeks. Sound too good to be true? Yes it does. However, the principals have the credentials to back up the boast, and a customer list that includes a mobile LTE physical layer chip that is already on the market.
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