Altera developed a 4 chip MCM in the 90's with very little success due to availability of tools to wring out efficiencies in the design. It is likely the same problems will be seen with this new package.
We continue to enhance our Quartus II software to simplify the development of our devices, which includes enhancements that enable the development of 2.5D devices (integrating multiple FPGA die in a package leveraging an interposer). Due to the large number of challenges at all levels of multi-die design, silicon vendors and EDA vendors alike will need to work closely together to develop the next generation of EDA tools.
Yes, that is possible, but the size of the bypass capacitor is often application dependent, as you mentioned. Xilinx for instance has publically state that they may add bypass caps to their silicon interposer.
Altera has already started adding MPUs, DSPs, ASICs, ASSPs to its FPGAs making silicon convergence a fait accompli, but Waters point here is that with silicon interposers this ability now has a 3-D platform to take it mainstream.
I don't suppose it would be a cost-effective use of all that 3D space to incorporate the necessary decoupling capacitors?
The amount of real estate given to external capacitors 'just in case' is insane; the chip makers know how much capacitance it needs, so fit it insid and let the rest of us use the PCB for something that us actually useful to our app.
Yes, I know, if we are pumping the I/O at LF we may need extra caps, credit us with _some_ design skills; what we don't have is PCB space, or indeed the extra layers needed to track past the decoupler arrays.
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