We decided to develop a system based upon the ZINQ7000. This entailed getting Vivado, and designing in that environment. We also got two weeks of training on the tool. What we found, was that the use of this tool greatly impacted our development time in a negative way. What was thought to be a 3 month development task turned into about 9 months. In addition, I received an email from a Xilinx engineer apologizing for the pain we were going through, and said that the release of 2014.1 had fixed over 9000 known bugs in the software package. I only have one question:
What kind of company releases a software package with over 9000 known bugs?
In the end, we ended up going with the Altera equivalent. Development on their platform (Quartus II) took about 4 months.
Well, since you have selected "Experienced Engineer" as your username, you must obviously be an experienced engineer.
Following the same line of reasoning, since I have "Magnificent" in my user name... well, I will let you draw your own conclusions.
I shall be using Vivado in the next few months - will report on my experience then. One thing is for sure, the Zynq architecture is a paradigm shift in FPGA architectures which might take this technology to a whole different level.
I have been an electronics engineer for over 40 years. During that that time I have worked with many engineers, with varying capabilities. The one thing I can state unambiguously is that those who were afflicted with an excessive egomania were uniformly substandard in their design ability. With that said, your self-reference to "Max the Magnificent" pretty much sums up the correctness of my observations. Your comments here, as well as some of the Readers Digest quality of your articles are very consistent with someone who lacks a fundamental grasp of electronics engineering and tries to mask this reality by declaring themselves "magnificent."
I believe that actually a potential customer would pay an ~$1800 increment over the Vivado Design Edition to get HLS in the System Edition.
However, the minimum price of an offering including HLS appears to be $4795 overall (targeting FPGAs; ASICs are a different matter).
Not that I have an axe to grind, but do you have any idea how much effort and resources it takes to construct a design suite of this complexity?
If you look at the size (capacity) and complexity of the new devices, it's obvious that previous generation tools would struggle to keep up in the not so distant future.
I personally am very impressed that Xilinx had the vision to start this effort almost 5 years ago -- long before the new devices were even tied down.
Propitiatory? Well, if you are selling your own chips with their own unique architecture and you are creating a design tool suite ... would you try to make your tool suite work with competitor devices?
Over-priced? Have you looked at the price of ASIC tools recently? The HLS in Vivado is a $2000 option -- orders of magnitude cheaper than the ASIC equivalent.
Where are the open-source tools? You start working on them and let me know when they are ready (grin)
What's all this ga-ga stuff over yet another over-priced, proprietary tool? Get a grip!
Where are the open-source tools for cross-platform development? Now THAT would be something to get excited about.
Replay available now: A handful of emerging network technologies are competing to be the preferred wide-area connection for the Internet of Things. All claim lower costs and power use than cellular but none have wide deployment yet. Listen in as proponents of leading contenders make their case to be the metro or national IoT network of the future. Rick Merritt, EE Times Silicon Valley Bureau Chief, moderators this discussion. Join in and ask his guests questions.