The way to go for an EDA start-up in FPGA software is up the tool chain. Remember when synthesis wasn't part of the vendors tool- just place and rout? How about making it easier to design at a higher level. Let me forget about constraint files, HDL languages, timing closure, and all that messy hardware stuff. The guys doing algorithmic design seem to be on the right path. We just need a different design model (maybe control + data flow) and get out of writing detailed code. Someone please help!
It is quite true decision of making the changes in the flow of the design process as 3D Architecture will require many new routing algorithms to be introduced and will required flexibility in the design flow.
If the cost of EDA software was standing in the way of adoption of FPGAs, then the silicon vendors would naturally have no choice but to break the logjam somehow.
Xilinx, Altera et al want to sell acreage of silicon real estate, and designers want it for their products, but the complexity and cost of the tools have been adding ever greater barriers to entry.
This situation has also existed in the ASIC world forever, but the setup costs, masks etc were still astronomical even if the EDA software had been free.