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KB3001
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re: Second generation for FPGA software
KB3001   6/6/2012 6:38:50 PM
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Economically, the EDA model is a difficult business model to execute successfully. The few companies that are succeeding in this market are offering complete domain solutions (hardware+API).

DrFPGA
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re: Second generation for FPGA software
DrFPGA   6/6/2012 5:08:21 PM
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The way to go for an EDA start-up in FPGA software is up the tool chain. Remember when synthesis wasn't part of the vendors tool- just place and rout? How about making it easier to design at a higher level. Let me forget about constraint files, HDL languages, timing closure, and all that messy hardware stuff. The guys doing algorithmic design seem to be on the right path. We just need a different design model (maybe control + data flow) and get out of writing detailed code. Someone please help!

Kinnar
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re: Second generation for FPGA software
Kinnar   4/30/2012 6:18:13 AM
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It is quite true decision of making the changes in the flow of the design process as 3D Architecture will require many new routing algorithms to be introduced and will required flexibility in the design flow.

agk
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re: Second generation for FPGA software
agk   4/28/2012 1:07:33 PM
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The Vivado can be easily used graphically or Tcl script language. So users can easily in a short time practice this.

Sanjib.A
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re: Second generation for FPGA software
Sanjib.A   4/28/2012 7:38:15 AM
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"Vivado is lot more open than their previous systems"...What is meant by 'open' for a FPGA development software?

KB3001
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re: Second generation for FPGA software
KB3001   4/28/2012 1:23:15 AM
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Unless standard and open high level languages are put forward, the barrier to entry will remain high IMO.

sharps_eng
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re: Second generation for FPGA software
sharps_eng   4/27/2012 10:29:19 PM
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If the cost of EDA software was standing in the way of adoption of FPGAs, then the silicon vendors would naturally have no choice but to break the logjam somehow. Xilinx, Altera et al want to sell acreage of silicon real estate, and designers want it for their products, but the complexity and cost of the tools have been adding ever greater barriers to entry. This situation has also existed in the ASIC world forever, but the setup costs, masks etc were still astronomical even if the EDA software had been free.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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