While scaling down exponentially to smaller and smaller sizes is the goal for engineers, if it makes no financial sense to do so, businesses would not fund that kind of development. Innovation here depends a lot on the profitability of making smaller and smaller chips. No one would want to spend so much resources to make a smaller chip if it doesn't have potential to make more money for chip makers.
Mary - http://www.jensenmarinedirect.com
Rick, if you or anyone else wants to better understand fully depleted (FD) planar or FinFET (3D) SOI (all very different from the partially depleted SOI IBM et al have long been using for high perf), lots of good info at www.soiconsortium.org. Also recommend an excellent white paper there posted by ST explaining their choice of FD-SOI for 28nm SOCs.
And ST-Ericsson's got a really interesting blog going on about it it (they tape out the new NovaThor smartphone SOC on 28nm FD-SOI in Q3) -- see http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/ . He says that FD-SOI at nominal voltages gives similar peak performance to HP processes and more than 35% performance improvement compared to LP at same Vdd; and it does far better on leakage & variability.
But I too would really like to hear more from anyone who was at the GSA Summit.
@rick.merritt: looks like you left before the GSA 3DIC Workgroup meeting that day where some interesting points were made (couple from myself!). While it is true that some companies (Samsung, Micron) are building 3DIC (TSV-enabled) memory products, the ecosystem challenge still remains as are the standards. There will be more discussions on these two at the upcoming GSA meetings.
I agree. I think this or a separate article needs to present the SOI portions of this GSA Silicon Summit. I did learn a lot about the merits of FD-SOI specially at low voltages. Items like ST is using this technology for 28 and 20nm were relevant. The numbers were actually impressive.
Frankly, yes the event was something of an SOI love fest. But it's a topic that has been around for years and one I (also frankly) don't have much perspective on.
So I focused on what seemed like the top issues I understand and are significant to a broad readership: The industry is moving to 3-D ICs, there is a debate about 20nm and the outlook for CMOS is hard but OK to 7 nm.
I'll let those interested in marketing SOI take out ads ;-)
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.