Existing (not optimally parallel) EDA tools can still exploit the operating system to benefit from parallelism. Examples abound, like the pattern-based DRC; in the TCAD area, computational lithography, etc.
FPGA-based accelerators enable to run chip designs at MHz speeds and to debug system-level scenarios in the lab, but they are not simulators. It is just a different product category.
- You can reach 1-10MHz speeds with them and therefore debug your driver and even your application in embedded systems
- They are very expensive.
- Require significant ramp-up time, and then if you change your code or libraries you are not really debugging your real silicon design
- Does not work alongside your existing test-bench (verification environment), and if it does you cannot reach MHz speeds.
- Limited in capacity (to scale you need to add more FPGAs/boxes but then you trade-off with speed)
- Lack support for non-synthesize-able code
- No support for 4-state logic
- Lack full visibility
- Long compilation time (require to synthesys and place-and-route)
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.