After the consolidation, innovation has slowed as they dealt with merging; which they still haven't completed yet, i.e. synopsys tools don't support system verilog evenly. Innovation seems to be changing the standard upon which the verification object library every 2 years (ovm, uvm, ouvm, double secret probation vm...) Innnovation is due in truly automated verification that combines design technique with automation, think what full scan meets atpg did for test; instead of more complicated aides to manual verification.....
EDA is unlike the other sectors quoted (fast food and household products) in that it spends its whole time cutting its own throat - let me explain.
Who is EDA's target market? Design Engineers. What do EDA products do for design engineers? They make those engineers more productive. So when the companies those design engineers work for are growing (selling more smart phones or memory chips or whatever) the number of design engineers does not grow because they are made more productive by EDA tools.
Hence the total number of seats for tools does not grow in proportion to the revenues of the electronics industry as a whole.
Growth areas therefore are: (1) new tool sectors ie solving new problems that the designer has not faced before; (2) new chip design companies (but they are put off by the huge cost of designing and producing chips and only a relatively small fraction succeed so only a small growth in active companies is seen). But neither of these will cause overall growth unless they outrun the erosion on pricing for existing tools.
It is not clear if the big 3 can tackle these areas, or whether they just continue to acquire startup companies who have tackled them.
If the markets need to see EDA as being a better investment, then I suggest paying dividends is a way to show real worth.
have you all forgotten that private equity made a bid for cadence as recently as 2007? it was in the $20+ range. Then cdns blew up and PE disappeared. SNPS was the better tgt - at the time their margins were lower, balance sheet was much better. yes you could milk one or more of these by cutting R&D...and you'd be left without much a couple nodes down the line
@John.Donovan: I do see some relevance of the Freescale example in this discussion. But I would like to point out that the private equity maneuvers on a semiconductor company and on an EDA company may not bear a one-to-one correlation. I can offer the example of MSC Software (not 100% in EDA except for their Emag software tools) that was taken private by a group of investors in the Silicon Valley and it seems to be panning out.
Rahul's arguments have merit but I question his conclusion. Private equity firms aren't looking for cash cows, they're looking for firms they can either build up and flip or sell off in pieces, neither of which applies to the Big Three EDA firms.
And ChipBuilder is right--Freescale is a cautionary tale. Even the money from their IPO last year was a drop in the bucket compared to what they still owe the equity firms that took them private.
The author's argument might have merit if any of the EDA companies could afford to go private by buying back all outstanding shares. But a standard private equity deal, a leveraged buy-out, does not strike me as a healthy move for any of the EDA companies. Yes they generate healthy cash flows, but that doesn't necessarily mean they should take on massive amounts of debt.
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...