Someone had better clue IBM to the hype factor. IBM Fellow Dr. Subramanian Iyer was showing cross sections of 32nm chips with 11 layers of metal, deep-trench capacitors for eDRAM, and TSVs at the recent GSA Silicon Summit. Mr. Hassan's article repeats all of the same arguments used more than 20 years ago to explain why surface-mount technology was doomed: can't rework the boards with a soldering iron, can't test the boards with through-hole testers, JTAG costs too much to add to chips, blah, blah, blah. That dismal prediction of failure seems to have been wrong.
There are too many technical advantages and too few disadvantages at this point for 3D IC assembly not to take off. Rather than labeling technical analyses as "hype" and "wishful thinking," how about a more fact-based argument to counter the technical advantages and the obvious, displayed progress by companies such as IBM and Xilinx?
The Raspberry Pi board uses a standard Broadcom BCM2835 SoC with POP (package-on-package)mounted DRAM. Nevertheless, every mobile phone handset out there already uses a 3D IC stack with wirebonding and has for years. So we're just talking a difference in interconnect here, as well as deciding who is responsible for and gets paid for a working 3D stack.
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This is an interesting analysis, but I have to say its more than the memory guys waiving the 3-D IC flag these days.
It's big logic and fab folks like Altera, IBM, Qualcomm, TSMC, Xilinx and others. Are they all drinking the Kool-Aid?
"..But alas, today's module is tomorrow's much lower cost IC. ..".
So true in the past but the 3D proponents are just hoping that Moores's Law will finally grind down if not for device fundamentals ( leakage ) then at least for lithography ( EUV ) or just the min. order size needed to justify a $ 10 billon Fab
I see most of the KGD work happening at the IDMs and most of the 3d packaging happening in conjunction with the packaging houses. The package (and sometimes test) houses will pretty much follow whatever the IDM's push but most packaging houses that I've seen don't really have much advanced test technology. This is likely to change as some of the bigger boys (like AMD) go more fabless. And to address another point, there is speed testing done at wafer level, particularly by captive processor module companies who don't want to throw away expensive chips. But alas, today's module is tomorrow's much lower cost IC.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.