The original explanation from Intel, why back when, was that the gate wrapped around three-sides of the rectangular cross-section fin.
If the fin is trapezoidal then tri-gate name is still ok, but if that fin is triangular in cross-section then perhaps Intel should go with bi-gate?
Makes sense. Consistent with
Intels 22nm chip voltage was raised to slightly greater than 1V vs foundry mobile parts that run 0.85 to 0.9V
b) intel 22nm parts having high leakage / leakage power.
I hope GSS publishes more on this topic. Very good work and helpful.
I spoke to my go to fab guy
He said the fin shape results from a gross electrical compromise to clear spacer off fin (required for the si and SiGe fin epitaxy). Vertical fins create better electrical uniformity and performance. But its very difficult to clear spacer off a vertical fin. He does not think this fin shape will work for foundry SOC chips. Too much electrical variation and leakage
the other driver for a tapered triangular Silicon FIN is to avoid / minimize ion implant shadowing in the source drain / graded drain ion implants ( if implanted ). A vertical FIN sidewall would likely introduce asymmetric and wafer rotational dependence on Source Drain offset with respect to the edge of the FIN channel. Another process latitude driver for FIN triangular shape.... ( ie not merely metrology )
Agree. Lower transistor threshold voltage results in faster but leaker part. If intel was taking all trigate leakage improvement and targeting performance, I don't understand why performance and or frequency is about the same? Ivy bridge frequency bins are only ~100Mhz higher vs 32nm sandy bridge. Clock frequency of 3.4 vs 3.5Ghz or performance benchmarking is less than I was expecting.
I still wonder if this trigate is really going to give intel a competitive advantage in mobile? Or is intel marketing misdirecting from their own short comings. Stock analysts in my opinion are often wrong but when I look at the data I think Gus Richards might be right.
Trigate has higher processing cost and extra design restriction (increases cost via larger die area). I looked at designing my I/O block with finfet (foundries name for trigate). Layout was larger (higher cost) and at block level my power was higher.
It will be interesting to watch if intel can make a better cell phone or tablet chip. But they better hurry since 28nm chips with improved power are ramping fast.
Finfets should provide power/perforamance advantage. Intel probably set their process to fit within a given power budget -- get as much performance as possible within that limit.
For example, lower transistor threshold voltages -- faster & more leakage. Intel would set process knobs like this to get as much performance as possible without blowing power limit.
For low power parts, Intel could set these knobs differently.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.