I suspect that the "triangle" shape represents some compromise between what is simple and reproducible to fabricate with regards to high volume manufacturing considerations, and what is the ideal shape from from an electrical standpoint. It is also a more mechanically robust shape for a relatively high aspect ratio structure (less likely to break due to vibration, etc.).
Avoiding sharp corners is always a good idea in silicon manufacturing due to electric field crowding in device operation...and even if you wanted sharp fin it would be difficult to make it always equally sharp hence yeild hit...I suspect 2012 pics were of the marketing types...Kris
Simplest way to put it, rectangles have one more corner than triangles. Besides process variation, corners tend to have leakage current affecting off-stage performance, such as Vt and Ioff. In addition, the equivalent width of the FinFET may be easier to scale and control in triangular shape than in rectangular shape. It will be interesting to see NMOS vs PMOS with various width and how the width scaling is done.
iniewski has it right on one aspect.
Avoiding sharp corners is plausible advantage.
The second aspect I suspect is the ability to measure sidewall roughness without sidewall afm - atomic force microscopy that taps laterally ( the old IBM AFM that was a poor machine ). Here with sloped sidewalls, a topview high resolution SEM electron microscope images sidewalls usefully, and a comventional AFM topview tapping more trivially gets the needed "sidewall" roughness quantitaitvely measured with little difficulty versus the challenging vertical 90deg sidewall. And manufacturing metrology ease and accuracy of roughness here, which is a critical device parameter, since the surface is ETCHED ( worst thing you normally might do for a desired atomically smooth surface )...
Hence I suspect nano- metrology aspects are the driver ( this being a process engineer's perspective, not theoretical in the slightest )
Perhaps it was intentional to flood the media with sketches& even SEMs of rt. angled fins so that the pretenders and knock off artists would be misled for a while. But the important thing is that the power consumption for Ivy Bridge ( 22 nm, FinFET ) is NOT yet significantly less than Sandy Bridge to get a foot in the door at the SoC for SmartPhones house.
Corner leakage is usually a problem, but so is reproducability and control. It is difficult to know from so little data, how much of this triangle approach is for leakage vs. process control (yield). If the power levels don't give a dividend it will all be for naught.
Don't these sloped fins cause a lot of variation?
The device channel orientation is random vs 110 for ideal finfet and 100 for planar (mobility and many sources of variation)
Fin thickness depends on sidewall slope....and fin thickness sets my leakage and device threshold voltage, right?
I have bee puzzled why everyone claims trigate lowers standby leakage BUT I don't see any improvement in standby power at the chip level for intels 22nm ivy bridge??
Could this be the reasons leakage improvement does not match expectation for "ideal trigate".
Finfets should provide power/perforamance advantage. Intel probably set their process to fit within a given power budget -- get as much performance as possible within that limit.
For example, lower transistor threshold voltages -- faster & more leakage. Intel would set process knobs like this to get as much performance as possible without blowing power limit.
For low power parts, Intel could set these knobs differently.
Agree. Lower transistor threshold voltage results in faster but leaker part. If intel was taking all trigate leakage improvement and targeting performance, I don't understand why performance and or frequency is about the same? Ivy bridge frequency bins are only ~100Mhz higher vs 32nm sandy bridge. Clock frequency of 3.4 vs 3.5Ghz or performance benchmarking is less than I was expecting.
I still wonder if this trigate is really going to give intel a competitive advantage in mobile? Or is intel marketing misdirecting from their own short comings. Stock analysts in my opinion are often wrong but when I look at the data I think Gus Richards might be right.
Trigate has higher processing cost and extra design restriction (increases cost via larger die area). I looked at designing my I/O block with finfet (foundries name for trigate). Layout was larger (higher cost) and at block level my power was higher.
It will be interesting to watch if intel can make a better cell phone or tablet chip. But they better hurry since 28nm chips with improved power are ramping fast.
the other driver for a tapered triangular Silicon FIN is to avoid / minimize ion implant shadowing in the source drain / graded drain ion implants ( if implanted ). A vertical FIN sidewall would likely introduce asymmetric and wafer rotational dependence on Source Drain offset with respect to the edge of the FIN channel. Another process latitude driver for FIN triangular shape.... ( ie not merely metrology )
I spoke to my go to fab guy
He said the fin shape results from a gross electrical compromise to clear spacer off fin (required for the si and SiGe fin epitaxy). Vertical fins create better electrical uniformity and performance. But its very difficult to clear spacer off a vertical fin. He does not think this fin shape will work for foundry SOC chips. Too much electrical variation and leakage
Makes sense. Consistent with
Intels 22nm chip voltage was raised to slightly greater than 1V vs foundry mobile parts that run 0.85 to 0.9V
b) intel 22nm parts having high leakage / leakage power.
I hope GSS publishes more on this topic. Very good work and helpful.
The original explanation from Intel, why back when, was that the gate wrapped around three-sides of the rectangular cross-section fin.
If the fin is trapezoidal then tri-gate name is still ok, but if that fin is triangular in cross-section then perhaps Intel should go with bi-gate?