In the university we worked (and they still do) on a similar approach for partial reconfiguration through the ICAP but that was handeled entirely by the FPGA itself. The maximum clock frequency for the ICAP was achieved with little FPGA resources consumption.
Seems to me that the tools have a long way to go to make dynamic reconfiguration something that most designs will be able to do. For example, the need to have the decoupling logic explicitly defined (if I'm reading the article correctly) is the type of thing I would expect to be handled automatically.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.