Embedded Systems Conference
Breaking News
Newest First | Oldest First | Threaded View
Andreas Mauderer
User Rank
re: System-level design of mixed-signal ASICs using Simulink: Efficient transitions to EDA environments
Andreas Mauderer   7/13/2012 9:29:04 AM
Hi Michael, Thank you very much for your questions. 1. HDL Coder does not perform any high-level synthesis in terms of scheduling, binding and allocation. Instead, HDL Coder performs a direct mapping between Simulink blocks and VHDL/Verilog constructs both for data-flow and control-flow dominated designs. The presented optimizations only address data-flow dominated designs. 2. For the same specification the word-length optimization will result in the same implementation as long as the same seed for the random number generator is used. Yet, you are addressing an interesting point, as small changes in the specification can result in completely different word-lengths in the implementation. The most important verification step here is the comparison between floating-point and fixed-point model. We achieve that by simulating both designs in Simulink using testbench stimuli that are representing the specified behavior of the design. After that, by considering the signal deviations, we examine if the fixed-point model still fulfills the spec. The verification between the Simulink model and the generated RTL code is also done simulation based. 3. For data-flow dominated designs, which are addressed by our optimizations, the resulting Simulink models and RTL implementations are verified as described above. Control-flow dominated implementations resulting from HDL Coder can be formally verified by property checking against properties that represent the specified behavior. I hope I answered your questions. If any more questions occur, please feel free to post them. Regards, Andreas

User Rank
re: System-level design of mixed-signal ASICs using Simulink: Efficient transitions to EDA environments
mdos   6/21/2012 9:39:25 AM
A couple of questions coming from not very clear issues in the article: 1. How well does this methodology HLS perform to designs with complex control flow? I only show a couple of statements about data-path dominated (I suppose stream-based) designs... 2. It seems that because you are using simulated annealing to convert from floating point to fixed point, you will be getting different implementations from the same spec. every time you run the tool! Isn't this a burden for verification groups? 3. I don't see any formal methods used in the translation flow, from simuling models down to HDL implementations. How do you guarantee the correctness of the functionality of results? Even more, how do you prove the implementation functionality matches that of the specification? b.r. Michael

old account Frank Eory
User Rank
re: System-level design of mixed-signal ASICs using Simulink: Efficient transitions to EDA environments
old account Frank Eory   5/30/2012 9:49:47 PM
Excellent article. This is the first I have read of mixed-signal code generated by Simulink being brought into Cadence's ADE. Nice work!

Top Comments of the Week
Like Us on Facebook

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

March 28 is Arduino Day -- Break Out the Party Hats!
Max Maxfield
Well, here's a bit of a conundrum. I just received an email from my chum David Ashton who hails from the "Unfinished Continent" Down Under. David's message was short and sweet; all he said ...

Bernard Cole

A Book For All Reasons
Bernard Cole
1 Comment
Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...

Martin Rowe

Leonard Nimoy, We'll Miss you
Martin Rowe
Like many of you, I was saddened to hear the news of Leonard Nimoy's death. His Star Trek character Mr. Spock was an inspiration to many of us who entered technical fields.

Rich Quinnell

Making the Grade in Industrial Design
Rich Quinnell
As every developer knows, there are the paper specifications for a product design, and then there are the real requirements. The paper specs are dry, bland, and rigidly numeric, making ...

Special Video Section
After a four-year absence, Infineon returns to Mobile World ...
A laptop’s 65-watt adapter can be made 6 times smaller and ...
An industry network should have device and data security at ...
The LTC2975 is a four-channel PMBus Power System Manager ...
In this video, a new high speed CMOS output comparator ...
The LT8640 is a 42V, 5A synchronous step-down regulator ...
The LTC2000 high-speed DAC has low noise and excellent ...
How do you protect the load and ensure output continues to ...
General-purpose DACs have applications in instrumentation, ...
Linear Technology demonstrates its latest measurement ...
Demos from Maxim Integrated at Electronica 2014 show ...
Bosch CEO Stefan Finkbeiner shows off latest combo and ...
STMicroelectronics demoed this simple gesture control ...
Keysight shows you what signals lurk in real-time at 510MHz ...
TE Connectivity's clear-plastic, full-size model car shows ...
Why culture makes Linear Tech a winner.
Recently formed Architects of Modern Power consortium ...
Specially modified Corvette C7 Stingray responds to ex Indy ...
Avago’s ACPL-K30T is the first solid-state driver qualified ...
NXP launches its line of multi-gate, multifunction, ...
EE Times Senior Technical Editor Martin Rowe will interview EMC engineer Kenneth Wyatt.
Flash Poll